Abstract: A majority charge carrier semiconductor structure including a relatively heavily doped n type support layer, a second n type layer formed on the support layer and having a relatively light doping, a p layer formed on the second n layer, and a third n type layer having a relatively heavy doping formed atop the p layer. When voltage means is applied between top and support layers principal current flow is by majority charge carriers in either direction determined by the polarity of a pre-determined voltage. Current flow occurs substantially below the critical electric field, and free of avalanche multiplication or tunneling. In alternate embodiments the doping impurity concentration may be varied to alternately provide a device wherein the magnitude of voltage reference which determines current flow in one direction or in the opposite direction may be symmetrical, asymmetrical or highly asymmetrical.

Abstract: An active circuit and method for increasing the operating range of circuit elements of the type connected between a power supply and a circuit element, the active circuit including a transistor having a base, emitter and a collector, the transistor having a breakdown voltage. The transistor is biased to provide a current path through it to the circuit element and to develop a voltage thereacross. The transistor and its biasing in combination are operative when the supply voltage exceeds a predetermined level to cause the transistor to breakdown. The breakdown voltage across the transistor opposes the supply voltage so that the operating range is increased and the actual voltage applied to the element does not exceed the breakdown voltage of the element.

Abstract: Schottky barrier diode semiconductor structure having a semiconductor body formed essentially of silicon and having a surface with an active device formed in the semiconductor body having collector, base and emitter regions and with at least two metals on said surface combining with the silicon to form an alloy of at least two metals and silicon which is in contact with the collector, base and emitter regions and also extends beyond the base region to form a Schottky barrier diode having a barrier height which is determined by the composition of the alloy.In the method, the alloy of at least the two metals in combination with the silicon is adjusted to modify the barrier height of the Schottky barrier diode so that a barrier height can be chosen ranging from between 0.64 and 0.835.

Abstract: Disclosed is a BCD arithmetic method and BCD arithmetic apparatus for use in a data processing system. The binary adder included in a data system for binary arithmetic operations is additionally utilized in the invention to provide BCD sign-magnitude addition and subtraction of packed digits. The apparatus is utilized to carry out the method steps of preconditioning one of the operands by adding a predetermined binary number to each BCD digit, performing a binary addition, and applying a decimal adjust to form the decimal arithmetic sum. Subtraction steps include performing a two's complement binary subtraction of each BCD digit, and applying a decimal adjust to form the decimal difference. The method and apparatus may be utilized with other base number systems having members which may be represented by a binary sequence that does not use all of the 2.sup.N binary combinations in the set.

Abstract: A bipolar collector-up dynamic memory cell of the type utilized for storing information by writing and alternately reading information on a word line in response to a bit signal input. The memory cell includes a semiconductor body of one conductivity type having a planar surface, and a first transistor formed in the body having emitter, base and collector regions. The emitter is coupled to the word line and the base is coupled to the bit signal input. The collector region is of opposite conductivity type and is formed in the body extending to the surface to form a junction boundary between the collector and the body capable of exhibiting capacitance thereacross. A second transistor is formed in the body having emitter, base and collector regions. The base region is coupled to the bit signal input.

Abstract: A method for fabricating a semiconductor diode array, utilizing an alignment tool to precisely position a plurality of diodes so that they can be bonded into a precision array. The alignment tool and a method for fabricating the tool are also disclosed.