Abstract: Method for forming metal oxide semiconductor structure with a precisely controlled channel formed by a combination of diffusion and implantation through a common mask.

Abstract: Metal oxide semiconductor structure having precisely grown channel with the source and drain isolated from each other by a PN junction.In the method, a double diffusion is carried out through the same opening in an oxide or insulating layer to obtain a very narrow precise channel region with minimum spreading and which can be utilized with a P-type substrate to provide PN isolation between the source and drain.

Abstract: A count of ten divider uses plural divide-by-two circuits, plural NOR gates and an inverter formed in a semiconductor body all of the foregoing being in a collector-up configuration.

Abstract: Semiconductor structure formed from a semiconductor body having an impurity of one conductivity type therein and having a major surface lying in a <100> plane. Moats are provided which extend through the major surface and have spaced side walls lying in a plane different from the <100> plane and at said surface define spaced islands. Layers of protective material are formed on the side walls of the moats. Regions of said impurity of one conductivity type and of greater concentration than that in the body extend downwardly into the body from the protective layers. An insulating material fills the moats and devices are formed in the islands. An insulating layer is formed on said surface and lead means is provided on the insulating layer and extends through the insulating layer to make contact to the devices and extends over the material in said moats to interconnect the devices in the spaced islands.

Abstract: Vacuum sputtering apparatus for treating articles having a housing forming a main vacuum chamber with a plurality of work stations therein. A lock chamber is provided in the main vacuum chamber through which articles can be inserted and removed. Means is provided in the main vacuum chamber for advancing the articles sequentially through the work stations in the main chamber so that as articles are being removed from the lock chambers, articles which have passed through the work stations can be removed from the main vacuum chamber through the lock chamber.In the method articles are introduced into the main vacuum chamber through a lock chamber, and they are intermittently progressively advanced through a plurality of work stations in the main vacuum chamber and then are removed through the lock chamber.

Abstract: A MOS semiconductor device and method for forming same, including a semiconductor body of first conductivity type having a planar surface, said body having spaced grooves therein opening through said surface with insulating material filling said grooves and extending to the surface of said body. Spaced source and drain regions of second conductivity type are formed in the body in areas between said grooves filled with insulating material extending to the surface, and providing a channel region therebetween. An insulating layer is formed on said surface, and having a portion of relatively precise thickness overlying the channel region. A layer of semiconductor material is formed on said portion of the insulating layer, a protective layer formed on said insulating layer and said layer of semiconductor material, and lead means formed on said protective layer and extending through said protective layer to contact said source and drain regions and said semiconductor layer.

Abstract: The buried layer of an integrated circuit is produced by use of a grated mask. The growth of silicon dioxide in the exposed areas of the grate forms a stepped surface. Thereafter ion implantation in these areas and then merging the implanted regions forms a single buried region having a corrugated surface on which an epitaxial layer is grown. Such corrugated surface reduces the defect regions in the epitaxial layer.

Abstract: A decode driver useful in decoders for memory circuits. A plurality of transistors are connected in series between a first reference potential terminal and an output terminal. A second plurality of transistors are connected in parallel between a second reference potential terminal and the output terminal. Each of the transistors receives an input which functions to turn the transistors either on or off. The coding of the inputs determines whether the transistors to which the respective inputs are connected are turned on or off which in turn controls whether or not the output terminal is coupled to the first reference potential terminal or the second reference potential terminal.

Abstract: An integrated circuit and method for forming the same including a lateral bipolar transistor having an increased current gain. Floating islands are formed in the emitter of the lateral transistor to have a conductivity type opposite that of the emitter and which act to channel current towards the periphery of the emitter, thereby directing the current towards the collector region. In addition, the integrated circuit includes a buried layer underlying the lateral transistor with the buried layer pinched very thin along a region which outlines the edge of the emitter for enhancing lateral current flow.

Abstract: A parallel shifter consists of a plurality of AND gates arranged in a skewed configuration to simulate the partial products of a multiplication of the binary number to be shifted with a second binary number representing 2.sup.N where N is the number of shift steps. Pseudo multiplication may be accomplished merely by ORing the outputs of the AND gates of any given binary weight since only one partial product of that weight will be non-zero. Left or right shift is accomplished by selection of the most significant or least significant half of the product. Rotation is accomplished by merging of the two halves.

Abstract: A high inverse gain semiconductor device including a one conductivity semiconductor substrate having a major surface and a buried region formed in said substrate of relatively high concentration one conductivity impurities extending to said major surface. A one conductivity semiconductor layer is formed on said major surface, said layer having a planar surface. An opposite conductivity base region is formed in said layer overlying said buried region and extends to said planar surface. The base region has an outwardly notched handle-shaped portion extending outward from said base region into said body and extending to said planar surface. A one conductivity additional region formed entirely within said opposite conductivity base region extends within said base region to form a relatively uniform base region exclusive of said handle-shaped portion having a relatively narrow base width between said additional region and said layer.

Abstract: A semiconductor memory cell, and a method for fabrication, including a one conductivity semiconductor body having a major surface and an opposite conductivity layer formed on said major surface said layer having a planar surface. Means extend from said planar surface through said layer to contact said body for isolating portions of said layer into first and second device regions. First and second device regions each include a one conductivity region formed in said device region extending to said planar surface, an opposite conductivity region formed within said one conductivity regions extending to said surface, and a metal-to-semiconductor contact carried by said device region at said planar surface. Lead means include means for ohmic interconnection of opposite conductivity regions formed in said first and second device regions, means for interconnecting said first device region and said one conductivity region formed in said second device region.

Abstract: A 4 .times. 4 multiplier uses four bit threshold logic type adders. The multiplier per se is arranged in a carry save configuration with first level pseudo type carry-look ahead with the highest weight bit of the product being accomplished by a wired OR connection. The four bit adder itself provides two double threshold detectors responsive to logic levels provided by a level shifter which shifts the logical voltage levels produced by a differential amplifier which sums the four inputs of the adder circuit. This provides the sum output; an additional double threshold detector provides the first carry output and a typical threshold AND gate the second carry output.

Abstract: Semiconductor structure formed of a semiconductor body having a planar surface and having regions of first and second conductivity types extending to the surface and with a layer of insulating material formed on the surface. The layer of insulating material has openings formed therein exposing portions of said regions. A lead structure is adherent to the layer of insulating material and extends through the openings to make contact to the portions of the regions so that the regions form parts of an integrated circuit. The lead structure includes a layer of gold having a relatively rough surface with a roughness scale ranging from 10 to 20 microinches so that photoresist will readily adhere thereto.

Abstract: A collector-up binary structure of the type having spaced semiconductor regions forming a plurality of active devices for interconnection as a binary circuit is disclosed. The structure includes a semiconductor body of one conductivity having a planar surface, and spaced first, second, third and fourth transistors formed in said body. Fifth, sixth, seventh and eighth transistors are included, said fifth and sixth transistors being formed in the base regions of said second transistor and said seventh and eighth transistors being formed in the base region of said fourth transistor. Lead means provides ohmic contact to each of the respective regions of the respective transistors and interconnecting means is provided for connecting the plurality of active devices as a binary circuit. A structure further including ninth and tenth source transistors is also disclosed.

Abstract: A low resistance closed feedback loop regulated current source for supplying a load, the source being of the type including a transistor having input and output electrodes respectively connected between voltage input and current output terminals, and said transistor having a control electrode. The feedback loop includes amplifying means having an output connected to the transistor control electrode and having first and second inputs providing differential current gain for signal current at said inputs and for maintaining minimum differential voltage between said inputs. First and second PN semiconductor structures having first and second electrodes and having dissimilar junction boundary areas are provided with the first electrodes of said structures being connected to the respective first and second inputs of the amplifying means. A resistor is provided connected between the second electrode of the structure having the greater boundary area and the second electrode of the remaining structure.

Abstract: Ion implanted resistor having a semiconductor body of one conductivity type and having a planar surface with a region of opposite conductivity type formed in the semiconductor body which is defined by a PN junction extending to the surface. One portion of the region of opposite conductivity type in cross-section has a greater depth than the remaining portion whereby there is provided a resistance whose effective value is the value given by the parallel resistance of said one portion and the remaining portion to thereby provide a resistor having a controlled temperature coefficient.

Abstract: Semiconductor devices containing integrated circuits are attached directly to external package leads by pressing simultaneously a plurality of groups of leads against bonding pads on a plurality of face-up semiconductor dice and heating the composite structures. Solder bumps on the bonding pads contain hard pedestals which prevent the overlying leads from being pushed into the faces of the semiconductor devices while the solder on the solder bumps melts to form the bonds between the leads and the underlying semiconductor dice. The process for carrying out this operation lowers significantly the cost of each packaged semiconductor device and the resulting structure is more reliable than structures of the prior art.

Abstract: Semiconductor structure having a semiconductor body with a planar surface. At least one region having an impurity therein is formed in the body and extends to the surface. A layer of insulating material is provided on the surface. Openings are formed in the layer of insulating material and expose said surface. The openings are defined by inclined side walls which extend at an angle with respect to said surface of less than 70.degree.. Contact means is carried by the surface and extends through the opening to form contact with the region. At least portions of the contact means have a slope which conforms generally to the slope of the side walls.In the method, two materials are utilized in which one material has an appreciably higher etch rate than the other material so that a slope is provided on the material having the lower etch rate.

Abstract: A high speed threshold switching integrated circuit including a transistor and an integrally formed tunnel diode connected in parallel between the base and emitter of the transistor. The heavy doping necessary for the tunnel diode is achieved through the use of ion implantation. A current pulse applied to the emitter-base contact of the integrated circuit causes no collector current to flow until the point at which the rising current pulse exceeds the peak current of the tunnel diode. As the tunnel diode goes into the negative resistance region the transistor is turned on and rapidly pushed into near saturation with a consequent rapidly rising collector current.