Abstract: A constant current source circuit includes a single differential amplifier having both voltage and temperature stabilization circuits. The voltage and temperature stabilization circuits operate on a feedback principle, each receiving an input from the differential amplifier, and each in turn providing a signal back to the differential amplifier to provide the desired stabilization. The resulting circuit is particularly adapted for use in battery-powered equipment, where substantial variations in both temperature and operating voltage are likely to occur.

Abstract: In a circuit including a transistor pair feeding separate loads at different load voltages, current gain modulation or Early effect is avoided by employing an operational amplifier to maintain the collector-base voltages of the transistors equal and thereby maintain their alpha current gains equal.

Abstract: 1. In a method for forming a semiconductor structure utilizing a semiconductor body, forming a grid structure in the semiconductor body, forming a support structure upon the grid structure, removing only a portion of the semiconductor body to provide a semiconductor body which has a substantially uniform thickness in the vicinity of the grid structure and in which the grid structure does not intercept the exposed surface of the semiconductor body, and forming additional grid structure in the semiconductor body joining the first named grid structure so that islands of semiconductor material are formed in the semiconductor body which are isolated from each other and from the support structure.23.

Abstract: Two independent power supplies for an I.sup.2 L or ISL logic array can be timed to turn on at different times by a simple RC network connected externally of the logic array. The differential timing is utilized to condition or set a bistable device in a predetermined initial desired state, without requiring an additional device terminal pin for that purpose.

Abstract: In a method of configuring an integrated circuit provided in a semiconductor body having a surface and spaced semiconductor circuits formed in the body, intercoupling means are formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits.

Abstract: A single flip flop is integrated with MOS circuitry which enables the single flip flop to be triggered by each of several individual clocked functions without interfering with one another. The flip flop responds only to low to high transitions of each clock signal input. This is accomplished by feeding back the flip flop output to each trigger circuit in such a way as to temporarily disconnect the trigger circuit from the flip flop during the time period between two successive low to high transitions of a particular clock signal, so that the flip flop can be triggered by other clocked functions without interference from the particular clock signal.

Abstract: Selective plasma vapor etching process for performing operations on a solid body formed of at least two different materials capable of being vapor etched exposed at, at least, one surface of the body, with the body being disposed in a chamber having a partial vacuum therein. A gas plasma is created within the chamber to produce active species of atoms and molecules so that these species come into contact with the surface of the body to chemically react at least one of the materials with active species from the gas plasma to form a gas-non-gaseous chemical reaction by controlling the concentration and reaction kinetics of specific species, and by controlling the activation energy of the etching reactions to produce a difference in rates between the materials so that the etching is more selective to one material over the other. The species is also controlled by the frequency of the electromagnetic energy.

Abstract: Method for making a semiconductor structure having isolated islands of semiconductor material from a semiconductor body by forming a first layer of insulating material on a surface of the body having a first support structure upon the layer of insulating material and then forming grooves in the semiconductor body which extend to the layer of insulating material formed from the semiconductor body. A second layer of insulating material is then formed on the exposed surfaces of the islands. A second support structure is then formed on the second layer of insulating material. Thereafter, the first support structure is removed and circuit devices are fabricated in the isolated islands.

Abstract: A protective circuit arrangement for three state bus drivers, incorporating insulated gate field effect transistors, affords protection against short circuiting of the output bus. The protective circuit senses the short circuit condition at the output bus of two push-pull output transistors and feeds back a signal to the input circuit of the ON transistor which reduces the input drive to that transistor and limits the output current through that transistor to a safe value.

Abstract: A bridge circuit for a measurement bridge of the type using four impedance arms provides an output referenced to ground which is a function of the impedances in the respective arms. The bridge circuit includes an impedance bridge comprising first, second, third and fourth impedance arms connected in series loop with first, second, third and fourth bridge terminals serially defined at the connections between the respective arms. A source of constant current is connected between the first terminal and ground. A driver is connected to bridge terminals other than the output terminal. The driver is responsive to bridge terminal signals to provide a bridge output which is a function of the impedances in the respective arms.

Abstract: A temperature compensated piezoresistive transducer includes a silicon body having a major top surface and an under surface. The body has generally parallel spaced first and second elongate slots formed therein extending through said top and under surfaces to define a center portion between said slots and first and second outer portions at the outward edge of the respective slots. The center portion is adapted to receive pressure to be measured. The body has an additional slot extending through the top and bottom surfaces and extending around the first, second and center portions to define the outer periphery of a transducer membrane with portions of the body remaining to integrally support the membrane. Plural piezoresistive elements having elongate and transverse dimensions are formed on the membrane. The elements are arrayed to receive compressive and tensile stress when pressure is applied.

Abstract: A semiconductor structure, and method for fabrication, including a semiconductor body of one conductivity type having a major surface. A layer of opposite conductivity material is formed on said surface, said layer having an upper planar surface generally parallel to said major surface. Spaced first and second collector regions are carried by said layer. A third one conductivity region is formed in said layer spaced from said first and second region and extending to an exposed surface of said layer. A fourth region of opposite conductivity type is formed within said third region and extends to an exposed surface of said layer. The layer, third and forth regions form the respective regions of an opposite conductivity--one conductivity--opposite conductivity type source transistor.

Abstract: Complementary silicon gate MOS structure formed of a semiconductor body of silicon having a major surface with a first region of N conductivity type formed in the body and extending to the surface and a second region of P conductivity type formed in the body and extending to the surface. A P-channel MOS device is formed in the first region and an N-channel MOS device is formed in the second region to provide complementary devices in the body. Each of the P and N-channel devices has a polycrystalline gate structure in which the polycrystalline material is doped with a P-type impurity to make possible the matching of threshold voltages of both devices.In the method, complementary MOS devices are formed by the use of two separate etching operations on the polycrystalline material and forming relatively thick layers of silicon type material on the semiconductor body in separate operations.

Abstract: A junction field effect transistor and a bipolar transistor are merged in a single composite device disposed within a single isolation region by the use of planar processing techniques. The device includes an annular source region formed within a semiconductor body portion constituting a collector zone. Within the central portion of the collector zone circumscribed by the annular source region there is formed an emitter zone nested within a region that constitutes both the drain region of the JFET and the base zone of the bipolar transistor. An annular channel region connects the annular source region and the central drain region. An annular region forming a semiconductor junction with the annular channel adjacent to the annular source region constitutes one of two gate regions of the JFET. The other gate region is constituted by the body portion serving as the collector zone.

Abstract: A metal contact system for an IGFET having shallow source and drain includes a refractory metal silicide layer forming low resistance ohmic contact to a silicon surface, a layer on the silicide layer of another refractory metal to serve as a barrier against diffusion of the interconnect metal, and a layer of interconnect metal over the diffusion barrier layer. The refractory metal layers are deposited by sputtering platinum or platinel for the first layer and titanium-tungsten for the second layer. In metal gate construction an additional layer of chromium is used as an etch resistant mask to protect the refractory metal layers from chemical attack when removing silicon nitride after it has been used initially as an oxidation mask and later as a sputtering mask.

Abstract: Logic circuitry provides predetermined logic outputs in response to logical combinations of inputs. The circuitry includes a plurality of input devices for receiving logic inputs and capable of assuming conduction states in response to the logic levels of said inputs. At least one output device is connected to two or more input devices. Means having predetermined logic levels is provided connected intermediate the input and output devices for controlling the conduction state of the output devices as a function of the input devices and the predetermined logic levels.

Abstract: A semiconductor transducer chip is flip-chip bonded to a semiconductor interface chip, which is mounted on the ceramic package. Thermal coupling between the package and the transducer chip is minimized by the small contact area between the transducer chip and interface chip. Micron size spacing between the spring membrane in the transducer chip and the interface chip produces squeeze film damping of the spring membrane.

Abstract: A collector-up binary structure of the type having spaced semiconductor regions forming a plurality of active devices for interconnection as a binary circuit is disclosed. The structure includes a semiconductor body of one conductivity having a planar surface, and spaced first, second, third and fourth transistors formed in said body. Fifth, sixth, seventh and eighth transistors are included, said fifth and sixth transistors being formed in the base regions of said second transistor and said seventh and eighth transistors being formed in the base region of said fourth transistor. Lead means provides ohmic contact to each of the respective regions of the respective transistors and interconnecting means is provided for connecting the plurality of active devices as a binary circuit. A structure further including ninth and tenth source transistors is also disclosed.

Abstract: A three-output level logic circuit in which in addition to zero and one binary logic levels a third off-logic level is provided in which the output impedance is relatively high to in effect isolate the switching circuit from a common line to which it is connected thereby allowing several switching circuits to be used in common without deleteriously affecting switching speed in an overall computer or calculator unit.