Abstract: A central processing unit capable of executing the IBM System/370 Universal Instruction Set is disclosed. The instruction set establishes the functional specifications for the processing unit, features of which include: 8-bit (byte) alphanumeric coding, 4-bit packed decimal coding (2 digits per byte), two's complement fixed-point binary arithmetic, two levels of indexing, sixteen 32-bit (4 byte) addressable general registers, four 64-bit floating point registers, and program status word and control registers. Principal features of the hardware architecture include the use of a single main data/instruction bus, transfers to and from the main bus being made under encoded microprogram control, and placement of the fixed-point binary arithmetic logic unit elements and the associated sixteen general registers on a single cascaded group of LSIC chips which operate under control of the microcode.

Abstract: A bistable switching circuit contains a pair of like-polarity input transistor circuits (Q1 and Q2) arranged in a differential configuration to receive a corresponding pair of input signals. A pair of like-polarity cross-coupled transistor load circuits (Q3 and Q4) complementary to the input transistor circuits are coupled to them. A pair of resistive elements (R1 and R2) are coupled between a voltage supply (V.sub.CC) and the load transistor circuits. An output transistor (Q5) complementary to the input transistor circuit has its control electrode and one of its flow electrodes coupled across one (Q4) of the load transistor circuits. When the input signals assume values capable of causing the output transistor to turn on, no current flows in the output transistor until regeneration occurs in the load transistor circuits -- i.e., until they switch states.

Abstract: A field-programmable logic array (FPLA) circuit of both the single level logic type containing a programmable AND/NAND gate array and the multiple level logic type containing a programmable OR/NOR gate array responsive to data from a programmable AND/NAND gate array has the programmable capability for enabling certain device pins to switch between functioning as data output pins and data input pins. A sequential logic FPLA circuit containing the basic elements of the multiple level logic device has a plurality of JK flip-flops for on-chip data storage. Selected flip-flops may be directly loaded from pins also operable for supplying output data, may be dynamically converted to function as D-type flip-flops, or may be asynchronously preset/reset to desired logic states. These features are all controllable through on-chip programmable circuitry.

Abstract: A semiconductor memory cell for a programmable read-only memory includes a polysilicon layer formed with laterally spaced surface regions which differ in impurity concentration and which form two back-to-back series diodes functioning as a programmable diode and an isolating diode. Because of the different impurity concentration, the diodes have different reverse-bias breakdown voltages. The programmable diode has the lower reverse-bias breakdown voltage. The high reverse-bias breakdown voltage of the isolating diode has the effect of blocking the parasitic current drain on the programming current.

Abstract: In a memory cell array of the kind including a memory cell capacitor and a memory cell transistor connected in series between a field plate line and a bit line, both the field plate line and bit line are precharged to the same potential level. The field plate line is connected to one input of a sense amplifier and the bit line is connected to the other input. The charge and discharge of the memory cell capacitor causes equal and opposite voltage changes on the field plate line and bit line. With respect to prior art the cell signal is increased by the amount of signal on the field plate line and when sensed against a reference signal which is about one-half the amount of the cell signal, the sensed signal is about twice that obtainable in the prior art.

Abstract: The edge profile of a silicon layer is shaped to have a gradual incline considerably less than 90.degree. by continuously reducing the amount of oxygen mixed with carbon tetrachloride in a reactive ion etching environment. The etching mode varies from complete isotropic etching when the amount of oxygen is maximum, to complete anisotropic etching when the oxygen content is zero.

Abstract: A logic circuit in which (1) a first bipolar transistor has a base, an emitter, and a collector coupled to a voltage/current source, and (2) a second bipolar transistor has a base coupled to the emitter of the first transistor, an emitter coupled to a constant voltage source, and a collector coupled to the voltage/current source contains operational control circuitry for preventing the second transistor from either turning off or normally going into deep saturation. Each transistor is typically an NPN device. The operational control circuitry may then comprise (1) first circuitry for providing current from the voltage/current source in a single current-flow direction to the collector of the second transistor and (2) second circuitry for providing current from the first circuitry in a single current-flow direction to the base of the second transistor. Optimally, the first circuitry prevents the second transistor from ever going into deep saturation.

Abstract: A method of fabricating a thick field oxide isolation layer employs dual photoresist layers and selective ion implantation. A thick field oxide layer is grown on a silicon wafer and is covered with a negative photoresist layer followed by a thicker positive photoresist layer. The positive photoresist layer is exposed through a mask and developed to leave a portion remaining where an aperture in the field oxide is to be made. Boron ions are implanted into the silicon wafer through the layers not covered by positive photoresist. The remaining positive photoresist and the underlying negative photoresist are removed to expose the field oxide, after which the patterned negative photoresist is used as a mask to etch a hole in the field oxide that is self-aligned between the boron implants.

Abstract: An arbiter circuit includes a latch made of two crosscoupled NAND gates, one of which is a Schmitt NAND gate, a difference detector, and two output NOR gates. The output of the latch is coupled to the difference detector and to one input of the NOR gates. The NOR gates receive another input from the difference detector. The difference detector is responsive to a voltage difference that exceeds one V.sub.BE, thereby blocking signals that originate in the latch during oscillating or metastable states of the latch, which may include rut pulses.

Abstract: A linear transconductance amplifier includes a differential transconductance amplifier stage and a differential correction amplifier stage. In order to achieve linear operation over a wide dynamic range, the nonlinearities generated in the transconductance amplifier stage are substantially cancelled by the nonlinearities generated in the correction amplifier stage. This is accomplished by cross-coupling the two stages and establishing the relative gain of the correction amplifier stage with respect to the transconductance amplifier stage such that the desired cancellation occurs. In a preferred embodiment, optimum cancellation occurs when the gain of the correction amplifier stage is substantially one-half the gain of the transconductance amplifier stage.

Abstract: A method of fabricating an array of high capacity memory cells comprises patterning a semiconductor surface to form memory cell areas; covering the memory cell areas with insulator; forming an ion layer of first conductivity type throughout the insulator; forming an ion layer of second conductivity type throughout the semiconductor surface; forming a first conductive pattern over the insulating layer to form a storage gate and to define a storage region extending to an isolation region and to define a transfer region spaced from the isolation region by the storage region; removing ions of first conductivity type from the portion of insulator above the transfer region and from other active areas; removing ions of second conductivity type from the transfer region and other active areas; diffusing ions of first conductivity type from the insulating layer to the storage region to produce in the storage region a shallow ion layer of first conductivity type and a deep ion layer of second conductivity type; and form

Abstract: A dynamic address translation unit for converting virtual or "logical" address values into real or "physical" address values. A translation Lookaside Buffer (TLB) stores physical addresses corresponding to a limited number of previously translated logical addresses. The available space in the TLB is divided into partitions, each of which stores address translation data for a particular user process. The TLB partition in current use is identified by the value stored in a user partition counter, which is also used to verify that certain process control information (stored in a stack memory location) associated with the partition matches the process control information for that user process which is currently in control of the central processing unit.

Abstract: A method of fabricating an array of high capacity memory cells comprises forming a transfer gate over each cell area spaced from an adjacent isolation region to define a storage region in the semiconductor surface between the transfer gate and isolation region and to define a bit line region on the other side of the transfer gate; forming a shallow ion layer of first conductivity type in the storage region self-aligned with the transfer gate; forming a deep ion layer of opposite conductivity type in the storage region self-aligned with the transfer gate; forming a storage gate over a portion of the storage region spaced laterally from the transfer gate to form a gap between the storage and transfer gates; and introducing ions of the first conductivity type into the portion of the storage region defined by the gap to at least neutralize some ions in the deep ion layer.

Abstract: A cabinet for a central processing unit, made up of a card cage and refrigeration unit, for mounting and cooling electronic components on a group of vertically-aligned, closely-spaced circuit boards. A source of recirculating, forced, refrigerated air is employed to remove the heat from the highly concentrated electronic components. For ease of maintenance, the refrigeration unit and the power supply unit take the form of independently removable modules, and the removable circuit boards are mounted in a readily accessable card cage which incorporates formed card guides which facilitate card removal and insertion.

Abstract: A temperature stable voltage reference utilizes an enhancement field effect transistor and a depletion field effect transistor each connected in series with a current source. A differential amplifier has its input terminals separately connected between each of the field effect transistors and their respective current supplies. An input terminal of the field effect transistor is utilized as the reference voltage and is also connected to the gate of one of the field effect transistors, the gate of the other field effect transistor being connected to a reference potential.

Abstract: An improved read-only memory arrangement for generating a differential output signal within the memory array itself incorporates a column of reference cell transistors and a single reference bit line within the same general area occupied by the memory cell transistors and memory main bit lines. Each word line is coupled to the gate of one of the reference cell transistors as well as to the gates of the memory cell transistors lying in the same row. The reference bit line voltage is maintained substantially midway between the high and low potential levels of the main bit lines to produce a differential output voltage for sensing purposes.

Abstract: A variable impedance circuit in which nonlinearities caused by the application of a signal are substantially reduced by the use of a feedback circuit for cancelling out the added input current due to the application of the input signal. By using a feedback circuit to obtain the desired improvement in linearity, the gain of the feedback loop can be tailored to obtain the necessary impedance range and output swing in a circuit capable of operating at relatively low power supply voltages.

Abstract: A Class "B" amplifier circuit in which Class "B" conversion takes place in a converter portion of the circuit in combination with a differential amplifier input circuit, rather than in the output stage. The converter modulates the DC bias current supplied to the differential amplifier input circuit as a function of the input signal, in order to achieve Class "B" operation. The output amplifier portion of the circuit includes a pair of complementary, series-connected transistors, each of which is connected in a common-emitter configuration. The disclosed circuit provides a high input impedance and excellent dynamic range.

Abstract: A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.

Abstract: A simple MOS voltage divider uses three enhancement MOS transistors, which includes one load connected to two drivers in parallel. The gate of one driver is connected to the output node, and the other two gates are connected to the supply voltage. The transistors have a common substrate.By proper choice of the transistor geometry only, the output node voltage can be made independent of the threshold and temperature variations for output voltages larger than one threshold and smaller than one-half the supply voltage. Moreover, the ratio between the output and supply voltages remains constant.