Patents Assigned to SII SEMICONDUCTOR CORPORATION
  • Patent number: 10191124
    Abstract: Provided is a sensor circuit that has little possibility of being accidentally put into a test mode in response to an external input of noise or the like. The sensor circuit includes a clock generation circuit configured to output a control signal that is used to control intermittent operation to a physical quantity detection unit, and to output a sampling signal in a sleep period, a potential detection circuit configured to detect a potential at an output terminal and to output a detection signal, and a clock control circuit configured to output a mode switching signal that is a command to switch the clock generation circuit to a test mode, when a given signal pattern is detected in data that is obtained by sampling the detection signal based on the sampling signal.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: January 29, 2019
    Assignee: SII Semiconductor Corporation
    Inventors: Tomoki Hikichi, Minoru Ariyama, Hironori Yano
  • Patent number: 10043848
    Abstract: In order to form a light receiving element having high reliability and a MOS transistor together on the same silicon substrate, after forming a gate electrode of the MOS transistor, a gate oxide film in a light receiving element forming region is removed. Then, a thermal oxide film is newly formed in the light receiving element forming region, and ion implantation is performed in the light receiving element forming region through the thermal oxide film such that a shallow pn junction is formed.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 7, 2018
    Assignee: SII Semiconductor Corporation
    Inventor: Toshiro Futatsugi
  • Patent number: 9997645
    Abstract: A package for an optical sensor device has a double-molded structure in which a first resin molded portion and a second resin molded portion are integrated. The first resin molded portion has a structure in which peripheries of a die pad portion on which an optical sensor element is mounted and a part of each of a plurality of leads are molded with a resin so as to be integrated, the part of each of the plurality of leads being embedded in and completely surrounded by the first resin molded portion. The second resin molded portion is molded over at least a portion of the first resin molded portion to form an outer shape of the package and has embedded therein and completely surrounds a part of each of the plurality of leads. A glass substrate having a filter function is bonded to an upper surface of the resin molded portions to form a cavity in which is mounted the optical sensor element.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: June 12, 2018
    Assignee: SII Semiconductor Corporation
    Inventor: Koji Tsukagoshi
  • Patent number: 9972625
    Abstract: Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 15, 2018
    Assignee: SII Semiconductor Corporation
    Inventors: Hirofumi Harada, Keisuke Uemura, Hisashi Hasegawa, Shinjiro Kato, Hideo Yoshino
  • Patent number: 9966476
    Abstract: A semiconductor memory device includes a first floating gate and a second floating gate of conductivity types with different polarities. Injection of electrons into the first floating gate via a tunnel insulating film is stored through a decrease in holes in a valence band of the second floating gate, and ejection of electrons from the first floating gate via the tunnel insulating film is stored through an increase in holes in the valence band of the second floating gate.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: May 8, 2018
    Assignee: SII Semiconductor Corporation
    Inventor: Tomomitsu Risaki
  • Patent number: 9948302
    Abstract: Provided is a level shift circuit capable of avoiding breakdown due to level shift operation. The level shift circuit includes: a floating power supply having one end connected to an output terminal; a circuit configured to receive a voltage of the floating power supply, a voltage of a low level power supply and first and second pulse signals from a pulse generating circuit, thereof to output first and second signals; and a logic circuit configured to receive first and second signals, thereby converting a signal that is input to the pulse generating circuit into a signal that fluctuates between a voltage at the one end of the floating power supply and a voltage at the other end thereof to output the converted signal.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: April 17, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Kosuke Takada
  • Patent number: 9947706
    Abstract: Provided is a semiconductor device having a light receiving element in which a plurality of photodiodes are formed on a top surface of a P-type semiconductor substrate, an insulating oxide film is formed on surfaces of the photodiodes 51 via a buried oxide film, and an SOI layer of single crystal silicon is formed between a photodiode and an adjacent photodiode via the buried oxide film for shielding unnecessary light.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 17, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Takeshi Koyama
  • Patent number: 9941787
    Abstract: A reference voltage generation circuit includes a bandgap reference circuit, a first resistive element and a second resistive element connected in series between the output node and a ground terminal, a third resistive element, a fourth resistive element, and a first switch connected in series between the output node and the ground terminal, and a second switch having one end connected to a connecting point of the first resistive element and the second resistive element, at which a reference voltage is generated, and the other end connected to a connecting point of the third resistive element and the fourth resistive element. A ratio between resistance values of the first resistive element and the second resistive element is equal to a ratio between resistance values of the third resistive element and the fourth resistive element. The first and second switches are turned on at power-on and turned off after the reference voltage is started.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 10, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Akihiro Kawano, Katsuya Goto
  • Patent number: 9941717
    Abstract: Provided is a battery device having high overcurrent detection current accuracy that suppresses increases in a resistance value of a charge/discharge path and in a manufacturing cost. A first charge/discharge control device is configured to monitor a charge/discharge current with a voltage generated across both ends of a charge/discharge control switch, and a second charge/discharge control device is configured to monitor the charge/discharge current with a voltage generated across both ends of a current sensing resistor. A field effect transistor forming the charge/discharge control switch is selected based on a desired ON resistance value. The charge/discharge control switch of the first charge/discharge control device includes a field effect transistor having the desired ON resistance value, and a charge/discharge control switch of the second charge/discharge control device includes a field effect transistor having an ON resistance value other than the desired ON resistance value.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 10, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Fumihiko Maetani
  • Patent number: 9935030
    Abstract: A first resin encapsulated body and a second resin encapsulated body are stacked to form a resin-encapsulated semiconductor device. The first resin encapsulated body includes: a first semiconductor element; an external terminal; inner wiring; and a first resin for covering those components, at least a rear surface of the external terminal, a rear surface of the semiconductor element, and a surface of the inner wiring are exposed from the first resin. The second resin encapsulated body includes: a second semiconductor element having an electrode pad formed on a surface thereof; a second resin for covering the second semiconductor element; and a metal body connected to the electrode pad, and is partly exposed from the second resin. The inner wiring and the metal body are electrically connected to each other.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 3, 2018
    Assignee: SII Semiconductor Corporation
    Inventor: Noriyuki Kimura
  • Patent number: 9933494
    Abstract: To provide a voltage detection circuit in which the influence on a detection voltage by semiconductor manufacturing variations is small and which is small in current consumption. A voltage detection circuit is provided which detects a voltage, based on an output signal of a detection circuit and outputs a detection signal. The detection circuit includes a first MOS transistor unit which allows a first current to flow, a second MOS transistor unit which allows a second current to flow, and a current voltage conversion unit which converts each of the first current and the second current into a voltage and outputs the same as the detection signal. A voltage characteristic of the first current and a voltage characteristic of the second current are configured so as to be crossed with each other at a predetermined voltage.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: April 3, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Makoto Mitani, Kotaro Watanabe
  • Patent number: 9933798
    Abstract: Provided is a voltage regulator configured to stably operate with low current consumption, and having good responsiveness. A delay circuit is provided between a transient response improvement circuit and a voltage amplifier circuit.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: April 3, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Yoshihisa Isobe
  • Patent number: 9923458
    Abstract: Provided is a booster circuit enabling improvement of efficiency of a stress test for a circuit to which a boosted voltage is applied. A voltage divider circuit is configured to have a voltage-dividing ratio that is variable depending on a test signal, and a limiter circuit is configured to clamp a voltage to a voltage higher than a boosted voltage in normal operation. In a test mode, the voltage divider circuit is controlled so that the boosted voltage becomes higher than that in the normal operation, and the limiter circuit clamps the boosted voltage, with the result that a booster section continuously operates.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: March 20, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Yasushi Imai
  • Patent number: 9923411
    Abstract: An electronic device includes: a light detection circuit having a first light sensor and a second light sensor each generating a photocurrent by photoelectric conversion, a resistive element which allows a difference between the photocurrents generated by the first light sensor and the second light sensor to flow, and a voltage detection circuit which detects a voltage generated by the flow of the differential photocurrent through the resistive element, said electronic device being controlled in operation by an output signal of the light detection circuit; a storing unit charged each time the electronic device is operated; and a rectifying element provided between the storing unit and the resistive element. A current with which the storing unit is charged is made to flow to the resistive element through the rectifying element.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: March 20, 2018
    Assignees: SII SEMICONDUCTOR CORPORATION, THE RITSUMEIKAN TRUST
    Inventors: Fumiyasu Utsunomiya, Takakuni Douseki, Ami Tanaka
  • Patent number: 9917573
    Abstract: To provide a voltage detection circuit which avoids unintentional on/off-control of an output transistor immediately after starting a power supply. A voltage detection circuit is configured to be equipped with a comparator which compares a detected voltage and a reference voltage, and an inverter which drives an output transistor, based on an output of the comparator and to supply the operating current of the inverter by a current source.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: March 13, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Masakazu Sugiura
  • Patent number: 9917055
    Abstract: A corrosion-resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. An array of intersecting metal lines forming windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. A silicon nitride film having a uniform thickness is formed on a front surface of the semiconductor device to prevent entry of moisture.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 13, 2018
    Assignee: SII Semiconductor Corporation
    Inventors: Yukihiro Imura, Yoshitaka Kimura, Masaru Akino
  • Patent number: 9912237
    Abstract: To provide a COT-controlled switching regulator capable of preventing an output voltage from excessively exceeding a desired voltage even though a light load is connected to an output terminal. A switching regulator of the present invention is configured to be equipped with a 100% DUTY detection circuit which detects a 100% DUTY at which a high-side switching element continues an on state for a prescribed time or more and outputs a detected signal to an output control circuit and to cause the output control circuit to turn off the high-side switching element when the output control circuit receives the detected signal therein.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: March 6, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Akihiro Kawano, Katsuya Goto
  • Patent number: 9910452
    Abstract: Provided is a reference voltage circuit capable of adjusting an arbitrary output voltage to have arbitrary temperature characteristics. The reference voltage circuit includes: a reference current generating circuit configured to convert a difference between forward voltages of a plurality of PN junction elements into current to generate a first current; a current generating circuit configured to use the first current generated by the reference current generating circuit to generate a second current; and a voltage generating circuit including a first resistive element and a second resistive element, the first resistive element being configured to generate a first voltage having positive temperature characteristics when the first current flows through the first resistive element, the second resistive element being configured to generate a second voltage having negative temperature characteristics when the first current and the second current flow through the second resistive element.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: March 6, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Kosuke Takada, Masakazu Sugiura
  • Patent number: 9904170
    Abstract: When a reticle is first used, the reticle is loaded in a projection exposure device and measured by either oblique measurement or random measurement, thereby avoiding the fear of uneven sampling and determining the reticle transmittance of the entire reticle as the parent population, without increasing the sampling count. The same effect can be obtained by making the measurement spot size, which is fixed in general, variable and by changing the angle of incidence in relation to the measurement spot size.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: February 27, 2018
    Assignee: SII Semiconductor Corporation
    Inventors: Michihiro Murata, Yutaka Gomi
  • Patent number: 9893073
    Abstract: A semiconductor nonvolatile memory element is used to form a constant current source in a semiconductor integrated circuit device. The semiconductor nonvolatile memory element includes a control gate electrode, a floating gate electrode, source/drain terminals, a thin first gate insulating film, and a second gate insulating film that is thick enough not to be broken down even when a voltage higher than an operating voltage of the semiconductor integrated circuit device is applied thereto, the first and second gate insulating films being formed below the control gate electrode. Thus, provided is a normally on type semiconductor nonvolatile memory element in which a threshold voltage can be regulated through injection of a large amount of charge with respect to the operating voltage from a drain terminal into the floating gate electrode via the second gate insulating film, and injected carriers do not leak in an operating voltage range.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: February 13, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Hirofumi Harada, Shinjiro Kato