Patents Assigned to SII SEMICONDUCTOR CORPORATION
  • Patent number: 9891649
    Abstract: A safe and low-cost voltage regulator is provided through simplification of a circuit configuration of a protection circuit. The voltage regulator has a configuration in which current output of the protection circuit, which serves as a signal indicating that the protection circuit has started to operate, is input to a control circuit configured to improve responsiveness of the voltage regulator.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 13, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Yoshihisa Isobe
  • Patent number: 9886045
    Abstract: To provide a voltage regulator equipped with an overcurrent protection circuit which needs not to separately adjust a limited current and a short-circuited current and is capable of collectively adjusting them. There is provided an overcurrent protection circuit equipped with an output current limitation circuit which distributes a current supplied from a transistor sensing an output current of an output transistor and controls a gate voltage of the output transistor by the distributed current to limit the output current. The overcurrent protection circuit is configured in such a manner that the current distributed from the transistor sensing the output current is varied according to the voltage outputted from the output transistor, and its distribution ratio is determined by a size ratio between elements.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: February 6, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Daiki Endo
  • Patent number: 9887171
    Abstract: A semiconductor device has a semiconductor chip adhesively bonded to a die pad. An area having large irregularities is formed on an upper side surface of the semiconductor chip to be covered by an encapsulating resin, and an area having small irregularities is formed on a lower side surface of the semiconductor chip, thereby improving adhesive strength between the semiconductor chip and the encapsulating resin and preventing penetration of moisture from outside.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: February 6, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Makoto Takesawa
  • Patent number: 9886052
    Abstract: Provided is a voltage regulator configured to suppress a fluctuation in output voltage even when a power supply voltage fluctuates, thereby realizing stable operation thereof. The voltage regulator includes a control circuit including a first input terminal connected to a drain of an output transistor, a second input terminal connected to a power supply terminal, an overshoot detection circuit connected to the first input terminal, and a power supply voltage detection circuit connected to the second input terminal, and being configured to cause a boost current to flow through an error amplifier circuit when an output voltage and a power supply voltage largely fluctuate with respect to a predetermined voltage.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: February 6, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Tsutomu Tomioka, Masakazu Sugiura
  • Patent number: 9887693
    Abstract: To provide a clock selection circuit capable of reducing clock omission generated when switching from a state of being synchronized with a first clock to a second clock. The clock selection circuit is equipped with a clock detection circuit which detects a first clock to output a detected signal, a switch which outputs the first clock when the detected signal is at a first level and outputs a second clock when the detected signal is at a second level different from the first level, and a one-shot circuit which outputs a one-shot pulse in response to switching of the detected signal from the first level to the second level. The output of the switch and the output of the one-shot circuit are added to be outputted as an output clock.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: February 6, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Kosuke Takada
  • Patent number: 9882469
    Abstract: To provide a booster apparatus capable of being configured without using a plurality of voltage generators and with a simple circuit. A booster apparatus is equipped with a voltage generator, a plurality of boosting capacitors connected in series with the voltage generator, intermediary capacitors, and switch circuits configured to perform switching control of connections between the voltage generator, the plurality of boosting capacitors and the intermediary capacitors.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: January 30, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Atsushi Sakurai, Hiroshi Saito
  • Patent number: 9875154
    Abstract: Provided is a non-volatile semiconductor storage device which can be downsized with a simple circuit without impairing the function of an error correcting section, and a method of testing the non-volatile semiconductor storage device. An error correction circuit is configured to perform error detection and correction of merely the same number of bits as data bits, and a circuit for performing error detection and correction of check bits is omitted to downsize the circuit. A multiplexer for, in a testing state, replacing a part of the data bits read out from a storage element array with the check bits, and inputting the check bits to the error correction circuit is provided. Thus, error detection and correction of the check bits are performed to enable shipment inspection concerning the check bits as well.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: January 23, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Masanori Miyagi, Taro Yamasaki
  • Patent number: 9865463
    Abstract: In a method of manufacturing a semiconductor device, a first photoresist layer is applied on a polycrystalline silicon layer formed on a semiconductor substrate. The first photoresist layer is then patterned and cured with UV rays. The polycrystalline silicon layer is etched, using the first photoresist layer as a mask, to form a gate electrode and a resistive film of the polycrystalline silicon layer. A second photoresist layer is applied on the cured first photoresist layer and patterned to form an opening portion exposing the first photoresist layer. Impurities are ion implanted through the opening portion in the polycrystalline silicon layer. The channeling of impurities implanted during the ion implantation is suppressed by the cured first photoresist layer.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 9, 2018
    Assignee: SII Semiconductor Corporation
    Inventor: Hitomi Sakurai
  • Patent number: 9864387
    Abstract: Provided is a voltage regulator which is not affected by a variation in output impedance of a reference voltage circuit, that is, which is configured to output voltage with a small change due to temperature. Two reference voltages respectively having positive and negative temperature coefficients are added together through transconductance amplifiers having large input impedances, respectively, and the resultant is amplified.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: January 9, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Yasuhiko Ogura, Kaoru Sakaguchi
  • Patent number: 9859795
    Abstract: To operate a plurality of abnormality detecting functions of a switching regulator with low power consumption and configure an occupied area of a semiconductor device to be reduced. A switching regulator is configured to be equipped with a comparison circuit, switch circuits, and a switch control circuit and to switch the switch circuits by control signals of the switch control circuit and realize a plurality of abnormality detecting functions by the one comparison circuit.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: January 2, 2018
    Assignee: SII Semiconductor Corporation
    Inventors: Akihiro Kawano, Katsuya Goto
  • Patent number: 9859885
    Abstract: An electronic circuit includes a first level shift circuit, a second level shift circuit, an internal circuit, a high voltage circuit, first and second transistors, and first and second protective circuits. The first and second protective circuits perform control the first and second transistors so as to make them non-conductive when at least one of a plurality of types of power supply voltages becomes equal to or less than a predetermined value.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: January 2, 2018
    Assignee: SII Semiconductor Corporation
    Inventors: Shunsuke Kubota, Hiroyasu Yoshizawa
  • Patent number: 9841471
    Abstract: A Hall element is integrated on a single substrate and is capable of cancelling offset voltage with a spinning switch configured to switch spinning current and capable of simultaneously detecting a horizontal direction magnetic field and a vertical direction magnetic field. The Hall element has a four-fold rotational axis and includes a P-type semiconductor substrate layer formed of P-type silicon, a vertical magnetic field detection N-type doped region formed on the P-type semiconductor substrate layer, and eight horizontal magnetic field detection N-type doped regions formed so as to surround the vertical magnetic field detection N-type doped region.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: December 12, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Takaaki Hioka, Mika Ebihara
  • Patent number: 9837960
    Abstract: Provided is an oscillation circuit that can limit a maximum value and a minimum value of a frequency even when some troubles are caused in a V/I conversion circuit. The oscillation circuit includes a current controlled oscillator configured to oscillate based on an input current, and a current limiting circuit configured to: compare the input current with a first constant current and with a second constant current; limit, when the input current reaches the first constant current, a maximum current value of the input current with a transistor arranged on a path of the input current; and limit, when the input current is lowered to the second constant current, a minimum current of the input current through addition of current on the path of the input current by a transistor arranged in parallel with the path of the input current.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: December 5, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Kosuke Takada
  • Patent number: 9837997
    Abstract: To provide a comparison circuit capable of removing the influence of an offset voltage of a comparator in the comparison circuit and obtaining a highly accurate comparison determination result even at a high temperature. A comparison circuit is equipped with a comparator including a first input terminal inputted with a first input voltage through a first capacitor and inputted with a third input voltage through a third capacitor, a second input terminal inputted with a second input voltage through a second capacitor and inputted with a fourth input voltage through a fourth capacitor, and an output terminal; a first switch which has one end connected to the first input terminal and is turned ON in a sample phase to switch the voltage of the first input terminal to a voltage of the output terminal; and a second switch which has one end connected to the second input terminal and is turned ON in the sample phase to switch the voltage of the second input terminal to a reference voltage.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: December 5, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Minoru Ariyama
  • Patent number: 9829904
    Abstract: To provide a low-pass filter circuit which is high in noise elimination capability and starts its output stably and at high speed, and a power supply device. A low-pass filter circuit is provided which is equipped with a capacitance element connected to an output terminal, and a resistance circuit connected between an input terminal and the output terminal, and in which the resistance circuit is equipped with a first MOS transistor connected between the input terminal and the output terminal, and an amplifier which has a first input terminal to which the input terminal is connected, a second input terminal to which the output terminal is connected, and an output terminal to which a gate of the first MOS transistor is connected, and which controls a time constant of the low-pass filter circuit.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: November 28, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Kaoru Sakaguchi
  • Patent number: 9831757
    Abstract: Provided is a voltage regulator configured to suppress a variation of an output voltage so as to stably operate even when a power supply voltage varies. The voltage regulator includes a control circuit having an input terminal connected to a drain of an output transistor, and an output terminal connected to an error amplifier circuit. The control circuit is configured to cause a boost current to flow through an error amplifier circuit when the output voltage varies beyond a predetermined value.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: November 28, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Tsutomu Tomioka, Masakazu Sugiura
  • Patent number: 9831176
    Abstract: A semiconductor integrated circuit device includes a fuse element that can be laser trimmed to adjust the characteristics of the semiconductor integrated circuit device, The semiconductor integrated circuit device includes an interlayer insulating film above the fuse element, and the thickness of the interlayer insulating film is reduced by using an amorphous silicon layer that is formed by sputtering as a material of the fuse element, and by forming the amorphous silicon layer at the same time as metal wiring is formed. The laser trimming processing is thus stabilized without needing a high level of dry etching stabilization control.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: November 28, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Hirofumi Harada
  • Patent number: 9829514
    Abstract: To provide a current detection circuit which suppresses a change in characteristics of a PMOS transistor on the non-inversion input terminal side of a differential amplifier due to NBTI and causes no change in threshold value at which an output voltage of the current detection circuit is inverted. A voltage limiting circuit which limits a voltage drop is provided between a non-inversion input terminal of a differential amplifier and a source of a PMOS transistor on the inversion input terminal side.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: November 28, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Toshiyuki Tsuzaki
  • Patent number: 9831845
    Abstract: There is provides a single conversion receiver and a communication system having wide occupied frequency bands and good receiving sensitivity.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: November 28, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Toshiyuki Tanaka
  • Patent number: 9829900
    Abstract: The voltage regulator includes an overheat protection circuit. The overheat protection circuit includes: a temperature sensing circuit; a voltage difference sensing circuit configured to output a current depending on a voltage difference between a power source voltage to be supplied to a power supply terminal and the output voltage; an output current monitoring circuit; a second reference voltage circuit configured to generate a second reference voltage; a comparator circuit configured to compare an output voltage of the temperature sensing circuit and the second reference voltage to each other; and an overheat protection transistor is configured to turn off the output transistor when the result of the comparison indicates an overheated state. The second reference voltage of the second reference voltage circuit is controlled based on an output current of the voltage difference sensing circuit and on an output current of the output current monitoring circuit.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: November 28, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Teruo Suzuki