Patents Assigned to SII SEMICONDUCTOR CORPORATION
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Patent number: 9748789Abstract: There is provided a battery device in which the accuracy of an over-current detection current value is high to have high safety. In a charging/discharging control circuit, a reference voltage circuit of an over-current detection circuit is configured to include a constant current circuit, a resistor, and a transistor having a resistance value that varies with a voltage of a secondary cell, that are connected to both ends of the secondary cell, and outputs, as a reference voltage, a voltage that is generated due to the flowing of a current of the constant current circuit to the resistor and the transistor.Type: GrantFiled: March 10, 2014Date of Patent: August 29, 2017Assignee: SII SEMICONDUCTOR CORPORATIONInventors: Fumihiko Maetani, Toshiyuki Koike
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Patent number: 9748946Abstract: To provide a power supply switching circuit which avoids an increase in current consumption. A power supply switching circuit includes MOS transistors provided between power supply input terminals and an output terminal, which have gates connected to each other and backgates connected to each other and are connected in series.Type: GrantFiled: February 4, 2016Date of Patent: August 29, 2017Assignee: SII SEMICONDUCTOR CORPORATIONInventor: Masakazu Sugiura
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Patent number: 9746531Abstract: To provide a magnetic sensor circuit which does not output spike-like voltage errors to a signal processing circuit. A magnetic sensor circuit is provided which is configured so as to output an output signal to a signal processing circuit through a plurality of hall elements driven by a first switch circuit and a second switch circuit controlled by a second control circuit and in which the first switch circuit controls timings at which spikes occur in the output signal of each of the hall elements in such a manner that the timings are not the same, and the second switch circuit selects and outputs an output signal having a period of a timing free of the occurrence of a spike.Type: GrantFiled: March 2, 2016Date of Patent: August 29, 2017Assignee: SII SEMICONDUCTOR CORPORATIONInventor: Masao Iriguchi
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Patent number: 9741924Abstract: A magnetic sensor has a pair of Hall elements formed in spaced-apart relationship on a front surface of a semiconductor substrate. A die pad is bonded to a back surface of the semiconductor substrate and overlaps the Hall elements. The die pad has formed therein a magnetic converging plate holder having a recessed portion, and a magnetic converging plate having the same shape and size as the recessed portion is fitted in the recessed portion of the magnetic converging plate holder.Type: GrantFiled: February 23, 2016Date of Patent: August 22, 2017Assignee: SII Semiconductor CorporationInventors: Takaaki Hioka, Mika Ebihara
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Patent number: 9740222Abstract: To provide an overcurrent protection circuit which prevents an excessive current from flowing to an output terminal for a long time, and a semiconductor device and a voltage regulator each equipped with the overcurrent protection circuit. An overcurrent protection circuit is configured to include a first transistor which allows a current proportional to an output current flowing through an output transistor to flow, a constant current circuit which allows a reference current to flow, a comparison circuit which compares the current flowing through the first transistor and the reference current, and a control circuit which controls a gate of the output transistor by a signal outputted from the comparison circuit.Type: GrantFiled: April 22, 2015Date of Patent: August 22, 2017Assignee: SII Semiconductor CorporationInventor: Masakazu Sugiura
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Patent number: 9733284Abstract: To provide a current detection circuit capable of suppressing the occurrence of a large potential difference between input terminals of a differential amplifier circuit, and preventing degradation of input transistors. A differential amplifier circuit is equipped with a clamp circuit which limits gate-source voltages of a pair of PMOS transistors each having a bulk and a source connected to each other with the sources of the pair of PMOS transistors as input terminals.Type: GrantFiled: April 5, 2016Date of Patent: August 15, 2017Assignee: SII SEMICONDUCTOR CORPORATIONInventors: Atsushi Igarashi, Nao Otsuka, Masakazu Sugiura
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Patent number: 9733567Abstract: When a reticle is first used, the reticle is loaded in a projection exposure device and measured by either oblique measurement and random measurement, thereby avoiding the fear of uneven sampling and determining the reticle transmittance of the entire reticle as the parent population, without increasing the sampling count. The same effect can be obtained by making the measurement spot size, which is fixed in general, variable and by changing the angle of incidence in relation to the measurement spot size.Type: GrantFiled: September 21, 2015Date of Patent: August 15, 2017Assignee: SII Semiconductor CorporationInventors: Michihiro Murata, Yutaka Gomi
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Patent number: 9726714Abstract: To provide a sensor device which is capable of high temperature detection using self-heat generation without providing a dedicated terminal and suppresses an increase in cost with an increase in chip occupation area due to the addition of a test pad. A sensor device is configured to include an active logic switching circuit for switching an active logic of an output driver and perform a heating inspection while switching the active logic of the output driver during an inspection process with the output driver as a heat generation source.Type: GrantFiled: March 2, 2016Date of Patent: August 8, 2017Assignee: SII SEMICONDUCTOR CORPORATIONInventor: Tomoki Hikichi
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Patent number: 9728478Abstract: A first resin encapsulated body (25) and a second resin encapsulated body (26) are stacked to form a resin-encapsulated semiconductor device. The first resin encapsulated body (25) includes: a first semiconductor element (2); an external terminal (5); inner wiring (4); and a first resin (6) for covering those components, at least a rear surface of the external terminal (5), a rear surface of the semiconductor element (2), and a surface of the inner wiring (4) are exposed from the first resin (6). The second resin encapsulated body (26) includes: a second semiconductor element (7) having an electrode pad formed on a surface thereof; a second resin (8) for covering the second semiconductor element; and a metal body connected to the electrode pad, and is partly exposed from the second resin. The inner wiring and the metal body are electrically connected to each other.Type: GrantFiled: October 10, 2016Date of Patent: August 8, 2017Assignee: SII Semiconductor CorporationInventor: Noriyuki Kimura
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Publication number: 20170221878Abstract: When an ESD element is operated, for the purpose of suppressing heat generation and causing uniform current to flow through all channels of all transistors included in the ESD element, various substrate potentials existing in the transistors and the channels of a multi finger type ESD element are electrically connected via a low resistance substrate, and further, are set to a potential that is different from a Vss potential. In this manner, the current is uniformized and heat generation is suppressed through low voltage operation to improve an ESD tolerance.Type: ApplicationFiled: July 8, 2015Publication date: August 3, 2017Applicant: SII Semiconductor CorporationInventor: Tomomitsu RISAKI
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Patent number: 9722538Abstract: Provided are a constant voltage circuit configured to, when a power supply voltage is low, detect a leakage current to output a stable voltage at a power supply voltage level, and a crystal oscillation circuit using the constant voltage circuit. The constant voltage circuit includes a leakage current detection circuit including a PMOS transistor for monitoring a leakage current, which has a gate and a source being grounded. When a leakage current is detected, even with a constant voltage power supply, a voltage sufficient for turning on an output transistor of the constant voltage circuit can be applied to a gate of the output transistor.Type: GrantFiled: February 4, 2016Date of Patent: August 1, 2017Assignee: SII SEMICONDUCTOR CORPORATIONInventors: Masaya Murata, Makoto Mitani, Kotaro Watanabe
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Patent number: 9720428Abstract: Provided is a voltage regulator having excellent transient response characteristics. The voltage regulator includes: a first switch connected between a gate of an output transistor and a phase compensation capacitor; a voltage follower having an input terminal connected to an output terminal of a differential amplifier; a second switch connected between an output terminal of the voltage follower and the phase compensation capacitor; and a comparator configured to compare a reference voltage and a feedback voltage. The first switch and the second switch are controlled with an output signal of the comparator.Type: GrantFiled: February 2, 2016Date of Patent: August 1, 2017Assignee: SII Semiconductor CorporationInventor: Teruo Suzuki
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Patent number: 9716190Abstract: An optical sensor device comprises an element-mounting portion, an optical sensor element provided on the element-mounting portion, a lead having a first contact region connected to the optical sensor element and a second contact region for an external connection, and a resin-encapsulating portion which covers at least a light-receiving plane of the optical sensor element. The resin-encapsulating portion comprises a resin and a glass filler including borosilicate glass dispersed in the resin. The transmissivity of the resin-encapsulating portion in one example is equal to or more than 40% in a wavelength range between 300 nm to 400 nm, and in another example is equal to or more than 60% in a wavelength range between 300 nm and 350 nm.Type: GrantFiled: March 18, 2016Date of Patent: July 25, 2017Assignee: SII Semiconductor CorporationInventors: Koji Tsukagoshi, Noriyoshi Higashi
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Patent number: 9716389Abstract: A power feeding system (100) includes a power feeding device (1) and a power receiving device (2). The power feeding device (1) includes: a drive transistor (13) connected to a feeding coil (11); a drive signal generation section (30) configured to generate a drive signal for driving the feeding coil (11); a crest value variation detection section (40) configured to detect the change in the resonant state of the resonant circuit (20) as a periodic waveform variation in a voltage excited in the feeding coil (11); and a drive control section (50) configured to determine whether or not electric power is suppliable to the power receiving device (2) based on the periodic waveform variation, and control to whether or not to continuously supply the drive signal to the drive transistor (13) based on a result of the determination.Type: GrantFiled: September 24, 2014Date of Patent: July 25, 2017Assignee: SII Semiconductor CorporationInventor: Norihiro Okazaki
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Patent number: 9704771Abstract: Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no oxide film exists on the scribe region so as to eliminate the interface between the oxide film that remains on the scribe region and the silicon substrate from which a crack may develop. As a result, the circuit board, the encapsulant, and the silicon substrate are stacked at an end portion of the semiconductor chip.Type: GrantFiled: October 29, 2015Date of Patent: July 11, 2017Assignee: SII Semiconductor CorporationInventors: Yoichi Mimuro, Kotaro Watanabe, Yukimasa Minami
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Patent number: 9698147Abstract: A semiconductor integrated circuit device has a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate. The first N-channel type high withstanding-voltage transistor includes a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor includes a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors are capable of operating at 30 V or higher and are integrated on the N-type semiconductor substrate.Type: GrantFiled: February 23, 2016Date of Patent: July 4, 2017Assignee: SII Semiconductor CorporationInventors: Hirofumi Harada, Keisuke Uemura, Hisashi Hasegawa, Shinjiro Kato, Hideo Yoshino
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Patent number: 9698064Abstract: A semiconductor device uses a lead frame, in which an outer lead is electrically connected to an inner lead suspension lead via an inner lead. An encapsulating resin covers the inner lead and part of the outer lead, and a plated film is formed on an outer lead cut surface so that a solder layer is easily formed on all surfaces of the outer lead extending from the encapsulating resin. The inner lead suspension lead includes a narrowed portion that is smaller in cross-sectional area than other portions of the inner lead suspension lead to suppress impact forces generated when the inner lead suspension lead is cut.Type: GrantFiled: March 11, 2015Date of Patent: July 4, 2017Assignee: SII Semiconductor CorporationInventor: Yasuhiro Taguchi
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Patent number: 9694523Abstract: A semiconductor device manufacturing apparatus for encapsulating with a resin a semiconductor chip includes upper and lower molds configured to receive therebetween a lead frame on which the semiconductor chip is mounted. A positioning pin provided to the lower mold is configured to be received by a positioning hole provided in the lead frame. Ejector pins provided in proximity to the positioning pin are arranged so as to be symmetrical with respect to the positioning pin.Type: GrantFiled: February 26, 2016Date of Patent: July 4, 2017Assignee: SII Semiconductor CorporationInventors: Yasuo Terui, Masaru Akino
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Patent number: 9691914Abstract: The following configuration is adopted in order to provide a highly reliable optival sensor device which enhances the reliability of devices without making the devices unsuitable for size and thickness reductions. The light sensor comprises an element-mounting portion (3) having a cavity and a lid member closely attached thereinto, the lid member being composed of: a window (2) constituted of a phosphate-based glass to which properties approximate to a spectral luminous efficacy properties have been imparted by compositional control; and a frame (1) constituted of a phosphate-based glass having light-shielding properties.Type: GrantFiled: January 27, 2015Date of Patent: June 27, 2017Assignee: SII Semiconductor CorporationInventors: Koji Tsukagoshi, Noriyoshi Higashi
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Patent number: 9679835Abstract: A resin-encapsulated semiconductor device comprises a semiconductor chip mounted on a die pad. A plurality of leads each having an inner lead and an outer lead are arranged in spaced relation from the die pad with the inner leads facing the die pad. A metal plating layer is formed on top surfaces of the inner leads, and the inner leads are connected by metal wires to the semiconductor chip. An encapsulation resin encapsulates the semiconductor chip, die pad, metal wires and inner leads leaving the outer leads exposed. The outer edge of the metal plating layer coincides with the outer surface of the encapsulation resin and with the outer edge of the metal plating layer.Type: GrantFiled: June 17, 2015Date of Patent: June 13, 2017Assignee: SII Semiconductor CorporationInventors: Shinya Kubota, Masaru Akino