Patents Assigned to SII SEMICONDUCTOR CORPORATION
  • Patent number: 9831769
    Abstract: To provide a switching regulator equipped with a power supply monitoring circuit small in current consumption. A switching regulator is configured to intermittently operate a power supply monitoring circuit only for a prescribed period based on a signal turning on a switching element, which is outputted from an output control circuit.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: November 28, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Akihiro Kawano, Katsuya Goto
  • Patent number: 9818691
    Abstract: A corrosion resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. A metal lattice having a plurality of windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. Alternatively, a metal array having a plurality of independent light-shielding portions may be disposed over the fuse elements to prevent the laser light from adversely affecting circuitry on the front surface side of the semiconductor device.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: November 14, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Yukihiro Imura, Yoshitaka Kimura, Masaru Akino
  • Patent number: 9818832
    Abstract: Provided is an integrated circuit having a LOCOS-drain type MOS transistor mounted thereon in which, even in the case of poor pattern formation, a withstand voltage is not lowered and a poor withstand voltage does not result. A drain oxide film thicker than a gate oxide film is formed on an active region on a drain side of the LOCOS-drain type MOS transistor, to thereby prevent the withstand voltage of the MOS transistor from being lowered even if the gate electrode reaches the active region on the drain side.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: November 14, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Yoichi Mimuro
  • Patent number: 9812958
    Abstract: A voltage regulator includes an error amplifier; an output transistor; and a first transistor including a gate for inputting a reference voltage and a source for inputting an output voltage. The first transistor is configured to cause a current to flow when the output voltage becomes an irregular voltage, and a current of the output transistor is controlled based on the current flowing through the first transistor. The voltage regulator capable of improving the overshoot or undershoot of the output voltage in a wide temperature range and to reduce a delay in detection of the overshoot or undershoot.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: November 7, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Fumiyasu Utsunomiya
  • Patent number: 9810746
    Abstract: To provide a magnetic sensor which is reduced in power consumption without reducing magnetism detection sensitivity of a magnetoelectric transducing element. One end of a magnetoelectric transducing element is connected to an output electrode of a constant current circuit, and the other end thereof is connected to a power supply electrode on the positive side of one or plural signal processing circuits, and the like built in a magnetic sensor, whereby a connection relation of the magnetoelectric transducing element and the signal processing circuit is configured such that they are connected in series with a voltage source.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: November 7, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Kentaro Fukai, Minoru Ariyama, Tomoki Hikichi, Takemasa Miura
  • Patent number: 9811105
    Abstract: To provide a reference voltage circuit capable of outputting a reference voltage excellent in temperature characteristic. A reference voltage circuit includes a first constant current circuit, a first transistor of a first conductivity type which has a source connected to the first constant current circuit and is operated as a first stage source follower, a second constant current circuit, and a second transistor of a second conductivity type which has a gate connected to the source of the first transistor and a source connected to the second constant current circuit and is operated as a second stage source follower. The reference voltage circuit is configured to output a reference voltage from the source of the second transistor.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: November 7, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Masakazu Sugiura, Tsutomu Tomioka
  • Patent number: 9812743
    Abstract: Provided is a battery state monitoring circuit and a battery device capable of predicting a state of charge of a secondary battery with high accuracy. The battery state monitoring circuit includes a pseudo-equivalent circuit of the secondary battery, and causes a current flowing through a sense resistor to flow to the pseudo-equivalent circuit of the secondary battery, to thereby measure a pseudo-open circuit voltage of the secondary battery.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: November 7, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Toshiyuki Koike, Kazuaki Sano, Atsushi Sakurai, Hiroshi Mukainakano
  • Patent number: 9804628
    Abstract: A reference voltage generator includes a depletion NMOS transistor of a first conductivity type for causing a constant current to flow, and an enhancement NMOS transistor of the first conductivity type diode-connected to the depletion NMOS transistor to generate a reference voltage. A resistor surrounds the periphery of the depletion NMOS transistor and the periphery of the enhancement NMOS transistor. A diode is connected in series to a constant current source and provides a voltage that controls current flowing through the resistor when the environment temperature is lower than a preset temperature. The reference voltage generator can operate under a given preset temperature environment because a voltage consumed in the resistor becomes approximately constant in accordance with the voltage provided from the diode.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: October 31, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Masayuki Hashitani, Yoshitsugu Hirose
  • Patent number: 9798346
    Abstract: Provided is a reference voltage circuit capable of outputting, with a low voltage and low current consumption, a voltage that is less liable to change due to a temperature change, and has a low GND terminal reference voltage. The reference voltage circuit includes a first NMOS transistor and a second NMOS transistor connected by a current mirror circuit, the first NMOS transistor having a gate and a drain connected to each other via a first resistor, the second NMOS transistor having a gate connected to the drain of the first NMOS transistor, and a source connected to a GND terminal via a second resistor, the second NMOS transistor having a threshold voltage lower than a threshold voltage of the first NMOS transistor, in which a reference voltage is output from the source of the second NMOS transistor.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: October 24, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Fumiyasu Utsunomiya
  • Patent number: 9800156
    Abstract: Provided are an amplifier circuit capable of improving phase characteristics, and a voltage regulator including the amplifier circuit. The amplifier circuit is configured to amplify an input voltage and to output the input voltage, and includes a current source, a first transistor having a gate to which the input voltage is applied, and a second transistor having a gate to which a voltage synchronous with the input voltage is applied, and a source connected to a capacitor.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 24, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Masakazu Sugiura
  • Patent number: 9798341
    Abstract: Provided is a voltage regulator including a clamp circuit capable of protecting a gate of an output transistor without limiting a drivability of the output transistor. The voltage regulator includes a level shift circuit having an input terminal connected to the gate of the output transistor and an output terminal connected to an input of the clamp circuit. The clamp circuit is controlled by an output voltage of the level shift circuit.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: October 24, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Tsutomu Tomioka
  • Patent number: 9800157
    Abstract: Provided is a switching regulator configured to suppress noise coupling, which may occur when a comparator is switched between a normal current operation and a low current consumption operation, to thereby operate stably. The switching regulator has a configuration in which switches are connected to input terminals of the comparator, and a feedback resistor having a large resistance value is disconnected from the input terminal of the comparator when switching is performed between the normal current operation and the low current consumption operation.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: October 24, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Akihiro Kawano, Katsuya Goto
  • Patent number: 9800149
    Abstract: To provide a switching regulator equipped with an on-time control circuit small in power consumption. An on-time control circuit is configured to be equipped with switches each turned on/off by a signal controlling on and off of a switching element and be turned off during an off-time of the switching element.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: October 24, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Akihiro Kawano, Katsuya Goto
  • Patent number: 9793215
    Abstract: A semiconductor integratd circuit device includes fuse elements formed on an element isolation insulating film, and an insulating film, an interlayer insulating film and a silicon nitride film successively formed over the fuse elements. An opening region extends through the silicon nitride film into the interlayer insulating film above the fuse elements, and openings formed in the interlayer insulating film are positioned on both sides of middle portions of the fuse elements. The openings facilitate blowing off of the insulating film during laser cutting of the fuse elements, reducing physical damage to the element isolation insulating film under the fuse elements.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 17, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Yukimasa Minami
  • Patent number: 9791873
    Abstract: A semiconductor integrated circuit device includes a PMOS output element having a source electrode connected to a power supply terminal and a drain electrode connected to an output voltage terminal from which an output voltage is supplied. A voltage dividing circuit has resistors for dividing the supplied output voltage to produce a divided voltage. A reference voltage circuit generates a reference voltage and has a memory element whose threshold voltage determines the reference voltage. The reference voltage circuit has a regulating input terminal connected to the memory element to change the threshold voltage of the memory element. An error amplifier is supplied with the divided voltage and the reference voltage to generate a voltage that is applied to a gate electrode of the PMOS output element. The voltage is amplified depending on a difference between the divided voltage and the reference voltage.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: October 17, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Hirofumi Harada, Shinjiro Kato
  • Patent number: 9774194
    Abstract: Provided are a charge and discharge control circuit having a small circuit area and a compact battery device. A constant current circuit and an external resistor are connected to a voltage monitoring terminal so that a terminal voltage is pulled up or pulled down based on an external input. Moreover, output logic of a comparator and overcharge detection and overdischarge detection are switched based on the external input.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 26, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Shinya Fukuchi
  • Patent number: 9773926
    Abstract: An optical sensor device includes a resin sealing portion for sealing an optical sensor element fixed to an element-mounting portion. The resin sealing portion is constituted of a resin having mixed and dispersed therein a glass filler obtained by pulverizing a phosphate-based glass which has spectral luminous efficacy properties by composition adjustment and high heat resistance and weatherability. The optical sensor device is highly reliable and capable of accommodating size and thickness reductions in packages and has stable and hardly changeable spectral luminous efficacy properties.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: September 26, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Koji Tsukagoshi, Noriyoshi Higashi
  • Patent number: 9772365
    Abstract: Provided is a detection circuit configured to avoid erroneous detection that may occur immediately after a detection circuit is powered on. The detection circuit includes: an output transistor connected between a voltage input terminal and a voltage output terminal; and a load open-circuit detection circuit configured to detect an open circuit of a load connected to the voltage output terminal, in which an output circuit of the load open-circuit detection circuit includes a first transistor and a second transistor connected in series, the first transistor having a gate connected to the output transistor in common, the second transistor having a gate to which a signal indicating that the open-circuit of the load is detected, and in which the first transistor is in an off state when the output transistor is in an off state.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: September 26, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Masakazu Sugiura, Atsushi Igarashi
  • Patent number: 9768758
    Abstract: A comparison circuit includes a comparator having a first input terminal receiving a first input voltage through a first capacitor, and a second input terminal receiving a second input voltage through a second capacitor, and an output terminal. A first switch has one end connected to the first input terminal and is turned on in a sample phase to set a voltage of the first input terminal as a voltage of the output terminal. A second switch has one end connected to the second input terminal and is turned on in the sample phase to set a voltage of the second input terminal as a reference voltage. A third switch is turned on in a comparison phase to equalize voltages of the other end of the first switch and the other end of the second switch.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: September 19, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Minoru Ariyama
  • Patent number: 9761577
    Abstract: A semiconductor device includes a power element and a heat sensing element configured to detect a temperature of the power element. The power element includes lateral MOS transistors having drains, two of the drains being shorter in length than the remaining drains, and the heat sensing element has a rectangular shape and is disposed between the two shorter drains to accurately detect the temperature of the power element.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 12, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Kazuhiro Tsumura