Patents Assigned to SII SEMICONDUCTOR CORPORATION
  • Patent number: 9401615
    Abstract: A charging and discharging control circuit includes a switching circuit that controls the gate of a bidirectional conduction type field effect transistor; a first transistor of which the drain is connected to the drain of the bidirectional conduction type field effect transistor, the gate is connected to the source of the bidirectional conduction type field effect transistor, and the source and the back gate are connected to a first terminal of the switching circuit; and a second transistor of which the drain is connected to the source of the bidirectional conduction type field effect transistor, the gate is connected to the drain of the bidirectional conduction type field effect transistor, and the source and the back gate are connected to the first terminal of the switching circuit. The back gate of the bidirectional conduction type field effect transistor is connected to the first terminal of the switching circuit.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: July 26, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Satoshi Abe, Atsushi Sakurai
  • Patent number: 9400515
    Abstract: A voltage regulator is provided which can suppress an occurrence of overshooting in an output voltage at the time of starting a power source with a source voltage or the like. The voltage regulator includes an error amplifier circuit, an overshooting control circuit that is connected to the gate of an output transistor, and an ON/OFF circuit that controls ON and OFF states of at least the error amplifier circuit. Here, the ON/OFF circuit controls the overshooting control circuit so as to turn on the output transistor when a predetermined time passes after at least the error amplifier circuit is turned on at the time of starting the voltage regulator.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 26, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Tsutomu Tomioka, Masakazu Sugiura
  • Patent number: 9397088
    Abstract: In order to provide a semiconductor device having high ESD tolerance, a plurality of source wirings (22) are formed of metal films having the same shape and electrically connect a plurality of sources (12) to a ground voltage wiring (22a), respectively, a plurality of drain wirings (23) are formed of metal films having the same shape and electrically connect a plurality of drains (12) to an input voltage wiring (23a), respectively, and a plurality of gate wirings (21) are formed of metal films having the same shape and electrically connect a plurality of gates (11) to the ground voltage wiring (22a), respectively. Further, a back gate wiring (24) is formed of a metal film and electrically connects a back gate (14) to the ground voltage wiring (22a), and the back gate wiring (24) is separated from the source wiring (22) formed on the source (12).
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 19, 2016
    Assignee: SII Semiconductor Corporation
    Inventors: Koichi Shimazaki, Yoshitsugu Hirose
  • Patent number: 9397026
    Abstract: A semiconductor device comprises a semiconductor chip mounted on an island, and a plurality of leads spaced form the island and connected by wires to the semiconductor chip. An insulating film encapsulates the island, the semiconductor chip, the wires and the leads, and the insulating resin has a concave portion that is in contact with the leads. Each lead has a bottom surface exposed from the insulating resin, and the concave portion of the insulating resin exposes side surfaces which surround the bottom surface of each of the leads located under a bottom surface of the insulating resin. When the semiconductor device is soldered to a circuit board, the concave portion prevents contact between the solder and the insulating resin and improves self-alignment of the semiconductor device on the circuit board.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: July 19, 2016
    Assignee: SII Semiconductor Corporation
    Inventor: Tomoyuki Yoshino
  • Patent number: 9391064
    Abstract: In order to provide a semiconductor device having high ESD tolerance, a semiconductor device (IC) is formed so that: a ground voltage wiring (22a) is electrically connected at one end in a wiring direction thereof to a wiring (22b) extending from a ground voltage pad used for external connection; an input voltage wiring (23a) is electrically connected at one end in a wiring direction thereof to a wiring (23b) extending from an input voltage pad used for external connection; and the one end of the ground voltage wiring (22a) and the one end of the input voltage wiring (23a) are substantially opposed to each other across a center of an NMOS transistor (10).
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 12, 2016
    Assignee: SII Semiconductor Corporation
    Inventors: Koichi Shimazaki, Yoshitsugu Hirose
  • Patent number: 9385057
    Abstract: A semiconductor flat package has a semiconductor chip, leads connected to the semiconductor chip, and an encapsulation resin covering the semiconductor chip and partially covering the leads. Outer end surfaces of the leads are exposed from the encapsulation resin and covered with a plated layer, and a side end surface of the plated layer and a side end surface of the encapsulation resin are flush with each other. A material with good solder wettability is formed at a lead cut portion of the semiconductor flat package, to thereby improve solder connection strength with a circuit board. A solder fillet is formed from the lead cut portion of the semiconductor package, to thereby enable adaptation of solder automatic visual inspection after mounting.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: July 5, 2016
    Assignee: SII Semiconductor Corporation
    Inventor: Tomoyuki Yoshino
  • Patent number: 9384943
    Abstract: Provided is an ion generating apparatus. The ion generating apparatus includes opposed electrodes connected to a high-frequency power supply, and hence, even in a case where a cathode filament is broken, hydride gas can be ionized to generate hydrogen ion. Thus, a fluorine compound deposited in a source housing is reduced in vacuum, and gas containing fluorine generated due to the above-mentioned reduction reaction is discharged with a vacuum pump.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: July 5, 2016
    Assignee: SII Semiconductor Corporation
    Inventor: Kiyohiro Tsuru
  • Patent number: 9386246
    Abstract: To provide a small-area photoelectric conversion device without impairing a resolution switching function, signals for controlling output order control switches provided so as to correspond to photoelectric conversion elements are selected by an output order control circuit and a shift register. In this manner, the number of flip-flops forming a shift register is reduced.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: July 5, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Tsutomu Tomioka, Daisuke Muraoka
  • Patent number: 9385584
    Abstract: Provided is a voltage regulator including a leakage current correction circuit capable of keeping the accuracy of an output voltage of the voltage regulator even when an output voltage of a reference voltage circuit is decreased due to the influence of a leakage current. The voltage regulator includes: a reference voltage circuit configured to output a reference voltage; an output transistor configured to output an output voltage; a voltage divider circuit configured to divide the output voltage to output a feedback voltage; an error amplifier circuit configured to amplify a difference between the reference voltage and the feedback voltage, and output the amplified difference to control a gate of the output transistor; and a leakage current correction circuit connected to an output terminal of the voltage divider circuit. The leakage current correction circuit is configured to decrease the feedback voltage to prevent the output voltage from dropping at high temperature.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: July 5, 2016
    Assignee: SII Semiconductor Corporation
    Inventors: Yuji Kobayashi, Teruo Suzuki
  • Patent number: 9372489
    Abstract: Provided is a voltage regulator including a leakage current sink circuit capable of suppressing an influence of a leakage current of an output transistor at high temperature, and reducing power consumption of the voltage regulator at normal temperature. The voltage regulator includes: a reference voltage circuit configured to output a reference voltage; an output transistor configured to output an output voltage; a voltage divider circuit configured to divide the output voltage to output a feedback voltage; an error amplifier circuit configured to amplify a difference between the reference voltage and the feedback voltage, and output the amplified difference to control a gate of the output transistor; and a leakage current sink circuit connected to an output terminal and configured to be prevented from operating at normal temperature, and suppress an influence of a leakage current from the output transistor only at high temperature.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: June 21, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Yuji Kobayashi, Teruo Suzuki
  • Patent number: 9374007
    Abstract: Provided is a DC/DC converter that is capable of performing stable control without being affected by noise from an output voltage and without any malfunction and is capable of operating at a relatively constant frequency. The DC/DC converter includes an ON-timer circuit configured to input a control signal, which is synchronized with a signal input to a gate of an output transistor, and output an ON-time signal. The ON-timer circuit includes: a ripple generation circuit configured to generate and output a ripple component based on the control signal; an averaging circuit configured to output a signal obtained by averaging the ripple component; and a timer circuit configured to generate and output the ON-time signal based on the signal of the averaging circuit and the control signal.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: June 21, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Yoshiomi Shiina, Masayuki Uno
  • Patent number: 9374077
    Abstract: There is provided a semiconductor device capable of preventing the passage of current that is unexpected in a circuit operation even in the case of reverse connection, thus ensuring higher safety. The semiconductor device has a switch circuit which includes: a first transistor; a second transistor having a drain thereof connected to a drain of the first transistor, a source and a back gate thereof connected to a back gate of the first transistor, and a gate thereof connected to a source of the first transistor; and a third transistor having a drain thereof connected to the source of the first transistor, a source and a back gate thereof connected to the back gate of the first transistor, and a gate thereof connected to the drain of the first transistor.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: June 21, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Atsushi Sakurai, Hiroshi Saito
  • Patent number: 9366730
    Abstract: There is provided a battery voltage detector circuit which uses a multiplexer system and which is capable of reducing the influence of the deviation of a detected voltage attributable to a parasitic capacitance, thus improving the accuracy of voltage detection. The battery voltage detector circuit that monitors the voltages of a plurality of batteries connected in series includes a flying capacitor, a multiplexer switch that sequentially connects the flying capacitor to the plurality of batteries, a voltage detecting unit that detects the voltage of the flying capacitor, a first reference potential detecting unit connected to one terminal of the flying capacitor, a second reference potential connecting unit connected to the other terminal of the flying capacitor, and a control circuit that controls the multiplexer switch, the first reference potential connecting unit and the second reference potential connecting unit.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: June 14, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Kazuaki Sano
  • Patent number: 9367073
    Abstract: Provided is a voltage regulator capable of preventing an output voltage from being increased even when a leakage current flows in an output transistor. The voltage regulator includes a leakage current control circuit. The leakage current control circuit includes an NMOS transistor connected to an output terminal of the voltage regulator. When the output voltage of the voltage regulator increases due to the leakage current of the output transistor, the leakage current control circuit causes the leakage current to flow through the NMOS transistor, to thereby prevent an increase in output voltage.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: June 14, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Tsutomu Tomioka, Masakazu Sugiura, Daisuke Yoshioka, Hiroki Chuman
  • Patent number: 9369117
    Abstract: Provided is a voltage regulator which consumes low power and uses an NMOS transistor as an output transistor. A delay circuit includes, between a constant current circuit and a capacitor, a depletion type NMOS transistor having a gate and a back gate each connected to a ground terminal, the constant current circuit including a depletion type NMOS transistor and a resistor connected between each of a gate and a back gate of the depletion type NMOS transistor and a source thereof.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 14, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Yotaro Nihei, Tomoyuki Yokoyama
  • Patent number: 9367074
    Abstract: Provided is a voltage regulator configured to suppress overshoot and undershoot so as to output a stabilized voltage. The voltage regulator includes: a high pass filter configured to detect a fluctuation in power supply voltage; a high pass filter configured to detect a fluctuation in output voltage; transistors connected in series, which are each configured to cause a current to flow in accordance with an output of corresponding one of the high pass filters; and a clamp circuit configured to clamp a drain voltage of one of the transistors connected in series. The voltage regulator controls a gate voltage of an output transistor based on a drain voltage of a transistor that includes a gate controlled by the drain voltage of the one of the transistors connected in series.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: June 14, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Tsutomu Tomioka, Masakazu Sugiura
  • Patent number: 9362195
    Abstract: Provided is a semiconductor device including a package having a hollow portion, which can meet the need of reduction in size and thickness. The semiconductor device includes: a resin molded member (1) including a hollow portion (10) having an inner bottom surface on which a semiconductor chip (6) is mounted, a surrounding portion (1b) that surrounds the hollow portion (10), and a bottom surface portion (1a); an inner lead (2e, 2f); and an outer lead (2a, 2b) exposed from the resin molded member (1). The inner lead buried in the molded member (1) includes an L-shaped lead extending portion having a through hole formed therethrough.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 7, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Koji Tsukagoshi, Sadao Oku, Hiroyuki Fujita, Keiichiro Hayashi, Masaru Akino
  • Patent number: 9354279
    Abstract: Provided is a magnetic sensor device, which is configured to connect each terminal of a Hall element to another end of a variable resistor having one end connected to GND by switching of four switches. Thus, a detection voltage level for a magnetic field intensity can be arbitrarily set with a small-scale circuit. The detection voltage level is determined only by the resistance ratio, and hence the influence of fluctuations in power supply voltage and manufacturing fluctuations can be suppressed. This configuration can simplify signal processing and achieve higher-speed signal processing.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: May 31, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Daisuke Muraoka
  • Patent number: 9348350
    Abstract: Provided is a voltage regulator including an overcurrent protection circuit in which an output voltage-output current characteristic exhibits an optimal fold-back characteristic even when an overcurrent state is detected. The overcurrent protection circuit includes a control circuit for generating a current in accordance with an output voltage, and controls a gate of an output transistor with use of a current obtained by subtracting the current from a sense current flowing in accordance with an output current.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 24, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Fumimasa Azuma
  • Patent number: 9343915
    Abstract: The semiconductor device includes the charging system including: electric power generating unit for supplying electric power; electric power storing unit for storing electric power generated by the electric power generating unit; switch unit provided in a charging path for charging the electric power storing unit with the electric power generated by the electric power generating unit; a comparator driven by the electric power generated by the electric power generating unit for comparing a reference voltage and a stored voltage of the electric power storing unit; and a level converter provided between the comparator and the switch unit for, based on a result of a comparison made by the comparator, converting a level of a generated voltage to a level of the stored voltage and outputting a resultant signal to the switch unit.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: May 17, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Makoto Mitani, Kotaro Watanabe