Patents Assigned to SII SEMICONDUCTOR CORPORATION
  • Patent number: 9467163
    Abstract: A high-order delta-sigma modulator is realized with amplifying/integrating circuits each having a small circuit scale, to thereby provide a small-size and low-power consumption delta-sigma modulator having a high precision. The delta-sigma modulator including the amplifying/integrating circuits connected in series in a plurality of stages has a delta-sigma modulator configuration in which one of adjacent amplifying/integrating circuits includes a delay integrating circuit and another thereof includes a non-delay integrating circuit. In an actual circuit, one amplifying circuit is operated in a time division manner to be shared between the adjacent amplifying/integrating circuits. The circuit scale is reduced in this way.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: October 11, 2016
    Assignee: SII Semiconductor Corporation
    Inventor: Eiki Imaizumi
  • Patent number: 9459641
    Abstract: Provided is a variable output voltage regulator capable of reducing heat generation during an overcurrent protection operation even when a setting value of an output voltage is high. The variable output voltage regulator can change an output voltage by trimming a resistor of a voltage dividing circuit in response to a trimming signal output from a trimming signal generation circuit. The trimming signal is used to change a limiting voltage of a fold-back type overcurrent protection circuit.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 4, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Kaoru Sakaguchi, Teruo Suzuki
  • Patent number: 9461038
    Abstract: A semiconductor device includes an insulated gate field effect transistor and a resistance circuit having a resistance element. The resistance element has a first thin film arranged on an isolation oxide film provided on a surface of a semiconductor substrate, a second thin film of silicon nitride formed on the first thin film so as to be wider than the resistance element, an intermediate insulating film of silicon oxide formed on the second thin film, a contact hole passing through the second thin film and provided in the intermediate insulating film at a depth reaching the first thin film, and a metal wiring formed in the contact hole. The insulated gate field effect transistor is provided in a region of the semiconductor substrate surrounded by the isolation oxide film.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: October 4, 2016
    Assignee: SII Semiconductor Corporation
    Inventor: Hirofumi Harada
  • Patent number: 9461632
    Abstract: Provided is a CR oscillator circuit that achieves a small occupied area and good oscillation frequency accuracy while having small current consumption. The CR oscillator circuit includes: a reference voltage circuit configured to switch and output a reference voltage; a first constant current source configured to charge a capacitor; a second constant current source configured to discharge the capacitor; a voltage comparator configured to compare voltages of the reference voltage circuit and the capacitor; and a logic circuit. The logic circuit is configured to switch between the reference voltage circuit and the constant current source simultaneously in response to an output signal of the voltage comparator.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 4, 2016
    Assignee: SII Semiconductor Corporation
    Inventor: Minoru Sano
  • Patent number: 9453888
    Abstract: The sensor device includes: a physical quantity voltage conversion element; a differential amplifier; a first capacitor that includes one terminal connected to a first output terminal of the differential amplifier; a comparator; a low pass filter circuit arranged at the first output terminal of the differential amplifier; a control circuit configured to on/off control the physical quantity voltage conversion element, the differential amplifier, the comparator, and the low pass filter circuit; and a logic circuit configured to output a result of operation processing performed on an output signal of the comparator. The logic circuit is configured to: successively verify, in a case where there is a change between a previous logic output and a first logic output, the logic outputs a plurality of times; and output a control signal to the control circuit so that the low pass filter circuit is turned on in a second signal processing period and thereafter.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: September 27, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Tomoki Hikichi, Minoru Ariyama, Kentaro Fukai, Takemasa Miura
  • Patent number: 9453889
    Abstract: To provide a magnetic sensor device which maintains accuracy thereof while reducing current consumption by switching drive power of a Hall element to two drive power. A magnetic sensor device is equipped with a driving circuit which supplies power to a sensor element, a switch changeover circuit which restricts the supply of the power from the driving circuit to the sensor element, a differential amplifier circuit which performs arithmetic processing on an output signal of the sensor element, a threshold voltage generating circuit which generates a threshold voltage used in magnetism determination, a comparison circuit which compares and determines a voltage of the differential amplifier circuit and the threshold voltage, and a logic circuit which according to the output of the comparison circuit, switches the power outputted from the driving circuit, switches the threshold voltage and controls on/off of the switch changeover circuit in a constant cycle.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: September 27, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Takemasa Miura, Minoru Ariyama, Tomoki Hikichi, Kentaro Fukai
  • Patent number: 9455628
    Abstract: To provide a voltage regulator capable of preventing a reduction in output voltage and an increase in output noise in a steady state without performing suppression of an overshoot. A voltage regulator is equipped with an overshoot detection circuit which detects an overshoot on the basis of an output voltage, an overshoot suppression circuit which controls an output terminal of an error amplifier circuit, based on the output of the overshoot detection circuit, and a driver state discrimination circuit which discriminates the state of an output transistor, based on an output voltage of the error amplifier circuit. The driver state discrimination circuit is configured to control the operation of the overshoot suppression circuit.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: September 27, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Tsutomu Tomioka, Masakazu Sugiura
  • Patent number: 9454174
    Abstract: Provided is a power supply voltage monitoring circuit capable of accurately detecting a power supply voltage with a small circuit scale and low power consumption. The power supply voltage monitoring circuit includes: a signal output circuit configured to output a signal voltage representing saturation characteristics with respect to an increase in power supply voltage; and a signal voltage monitoring circuit configured to output a signal representing that the signal voltage of the signal output circuit is normal, the signal voltage monitoring circuit including: a PMOS transistor including a gate connected to an output terminal of the signal output circuit; a first constant current circuit connected to a drain of the PMOS transistor; and an inverter including an input terminal connected to the drain of the PMOS transistor.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: September 27, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Atsushi Igarashi, Nao Otsuka
  • Patent number: 9444451
    Abstract: Provided is a switch circuit capable of reliably controlling the transmission or interruption of a voltage of from GND to VDD to an internal circuit even when a positive or negative voltage is input to an input terminal. By adding PMOS transistors to NMOS transistors constituting the switch circuit and controlling gates of the PMOS transistors by a voltage of the input terminal, the transmission or interruption of the voltage of from GND to VDD can be reliably controlled.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: September 13, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Yutaka Sato
  • Patent number: 9444335
    Abstract: Provided is a switching regulator configured to achieve a 100% Duty state and reduce an occurrence of an overshoot. The switching regulator has a configuration in which a clamp circuit configured to dynamically generate a clamp level clamps an output voltage of an error amplifier in accordance with a peak value of a triangular wave signal.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: September 13, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Michiyasu Deguchi, Kosuke Takada, Tetsuya Makino
  • Patent number: 9437258
    Abstract: Provided is a data readout circuit capable of, even when a high voltage is applied during data read-out operation, preventing erroneous writing of the data and reading out the data correctly. The data readout circuit includes: a non-volatile storage element; a latch circuit including: an input inverter; an output inverter; and a MOS transistor; a first MOS transistor connected between the non-volatile storage element and the latch circuit; a second MOS transistor connected between the latch circuit and the first power supply terminal; a first bias circuit configured to bias a gate of the first MOS transistor; and a second bias circuit configured to bias the MOS transistor in the latch circuit, each of the first bias circuit and the second bias circuit being configured to output a predetermined bias voltage when the data in the non-volatile storage element is read out.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: September 6, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Makoto Mitani, Kotaro Watanabe
  • Patent number: 9437669
    Abstract: A semiconductor resistor circuit has resistor elements of a polycrystalline silicon thin film formed on an insulating film deposited on a semiconductor substrate. A high stress insulating film is formed on and covers the resistor elements and the insulating film exposed between the resistor elements. Metal wirings cover upper portions of the resistor elements. The high stress insulating film has a membrane stress that is higher than that of the metal wirings.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: September 6, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Hirofumi Harada, Masaru Akino
  • Patent number: 9431273
    Abstract: A resin-encapsulated semiconductor device includes a semiconductor element mounted on a die pad portion, a plurality of lead portions arranged so that leading end portions thereof are opposed to the die pad portion, and thin metal wires for connecting together electrodes of the semiconductor element and the lead portions. Those members are partially encapsulated by a resin. A bottom surface part of the die pad portion and a lead bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulation resin. After a cutout part devoid of the encapsulation resin is formed above a lead upper end part, a plating layer is formed on the lead bottom surface part and the lead upper end part.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: August 30, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Noriyuki Kimura
  • Patent number: 9424943
    Abstract: The present invention provides a data reading device capable of preventing erroneous writing during an operation of reading data from a non-volatile memory element. The data reading device includes a dummy reading circuit provided with a non-volatile memory element, the writing voltage of which is lower than that of a non-volatile memory element of a data reading circuit, and a state detection circuit that detects a written state of the non-volatile memory element of the dummy reading circuit. Upon detection of erroneous writing to the non-volatile memory element of the dummy reading circuit during a data reading operation, the data reading operation is immediately terminated.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: August 23, 2016
    Assignees: SEIKO INSTRUMENTS INC., SII SEMICONDUCTOR CORPORATION
    Inventors: Kotaro Watanabe, Makoto Mitani
  • Patent number: 9425789
    Abstract: Provided is a reference voltage circuit capable of forming optimal circuits for various modes of an electronic device. The reference voltage circuit includes, between respective transistors forming the reference voltage circuit and between the transistors and a power supply terminal, switching elements configured to switch a circuit configuration of the reference voltage circuit.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: August 23, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Fumihiko Maetani, Toshiyuki Koike
  • Patent number: 9417645
    Abstract: Provided is a voltage regulator capable of controlling an output voltage to a predetermined voltage quickly after an overshoot occurs in the output voltage. The voltage regulator includes: an overshoot detection circuit configured to detect a voltage that is based on an output voltage of the voltage regulator, and output a current corresponding to an overshoot amount of the output voltage; and an I-V converter circuit configured to control a current flowing through an output transistor based on a current controlled by an output of an error amplifier and a current flowing from the overshoot detection circuit.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: August 16, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Fumiyasu Utsunomiya
  • Patent number: 9412710
    Abstract: In order to prevent a crack from developing in an interlayer insulating film formed under a bonding pad due to impact forces, the bonding pad is formed so that small diameter metal plugs and large diameter metal plugs are arranged between a first metal film and a second metal film as an uppermost layer. Holes are formed in the centers of the larger diameter metal plugs and recessed portions are formed in surface areas of the second metal film above the large diameter metal plugs.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: August 9, 2016
    Assignee: SII Semiconductor Corporation
    Inventor: Sukehiro Yamamoto
  • Patent number: 9412780
    Abstract: An image sensor has photodiodes formed in a Si substrate and configured to prevent carriers generated at a deep position of the Si substrate from affecting adjacent photodiodes due to lateral diffusion (crosstalk between pixels). A modified layer is formed between adjacent photodiodes and at a depth below that of the photodiodes by a laser to generate a recombination level to thereby suppress crosstalk between pixels.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 9, 2016
    Assignee: SII Semiconductor Corporation
    Inventor: Takeshi Koyama
  • Patent number: 9411345
    Abstract: Provided is a voltage regulator capable of controlling an output voltage to a predetermined voltage quickly after an undershoot occurs in the output voltage. The voltage regulator includes: an undershoot detection circuit configured to detect a voltage that is based on an output voltage of the voltage regulator, and output a current corresponding to an undershoot amount of the output voltage; and an I-V converter circuit configured to control a current flowing through an output transistor based on a current controlled by an output of an error amplifier and a current flowing from the undershoot detection circuit.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: August 9, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Fumiyasu Utsunomiya
  • Patent number: 9401607
    Abstract: Provided is a charge and discharge control circuit and a battery device which ensure high safety, even when a charger is reversely connected. The charge and discharge control circuit includes a consumption current increase circuit for supplying a current from a power supply terminal to a ground terminal, the consumption current increase circuit including a switch circuit configured to be turned on in response to a detection signal from a charger reverse connection detection circuit, which indicates that a charger is reversely connected.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: July 26, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Toshiyuki Koike