Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Abstract: A system that provides a bimanual user interface in which an input device is provided for each of the users hands, a left hand (LH) device and a right hand (RH) device. The input devices are used in conjunction with a large format, upright, human scale display at which the user can stand and upon which the input devices are moved. The positions of the input devices on the display are marked by displayed cursors. The system detects the position of the input devices relative to the display and draws a vector corresponding to unfastened tape between positions of cursors of the corresponding input devices and pointing from the LH device to the RH device. By changing the state of the LH input device the unfastened tape can be fastened or pinned along the vector as the user moves the LH device toward the RH device. By changing the state of the RH device, the tape can be unfastened by moving the LH device away from the RH device. Straight lines are drawn by holding the RH fixed while the LH pins the tape.

Abstract: Switches are used to serially isolate connectors for peripheral devices on a bus. Bus speed is selected based on the number of peripheral devices coupled to the bus via the connectors. Switches are used in the bus to provide selected isolation of the connectors. In one embodiment, the bus is able to operate at higher speeds when fewer connectors are on the bus. A method of configuring the bus determines how many devices are coupled to connectors on the bus. Portions of the bus not having devices coupled to connectors are isolated by controlling the switches between on and off states.

Abstract: A multiprocessor system and method includes a processing sub-system including a plurality of processors in a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store exclusive read-only copies of data from the processor memory system for use by a corresponding peripheral device.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: Mapping of cacheable memory pages from other processes in a parallel job provides a very efficient mechanism for inter-process communication. A trivial address computation can then be used to look up a virtual address that allows the use of cacheable loads and stores to directly access or update the memory of other processes in the job for communication purposes. When an interconnection network permits the cacheable access of one host's memory from another host in the cluster, kernel and library software can map memory from processes on other hosts, in addition to the memory on the same host. This mapping can be done at the start of a parallel job using a system library interface. A function in an application programming interface provides a user-level, fast lookup of a virtual address that references data regions residing on all of the processes in a parallel job running across multiple hosts.

Abstract: A method and apparatus for accessing memory-mapped registers that are distributed across a large integrated circuit. Some embodiments provide a method for accessing memory-mapped registers that are distributed across a first integrated circuit, the first integrated circuit including a plurality of logic subset modules, wherein each of the plurality of logic subset modules includes one or more memory-mapped registers. This method includes receiving a memory-mapped register access request into the first integrated circuit, serially transmitting, through each of the plurality of logic subset modules, a first plurality of data packets based on the memory-mapped register access request, wherein the first plurality of data packets includes an address specification for a memory-mapped register associated with a first one of the logic subset modules, and within the first logic subset module, accessing the memory-mapped register associated with the first logic subset module.

Abstract: The present invention provides a system for efficient, high speed, high bandwidth, digital communication where transmit distances are greater than a single clock period. The digital system operates based on a system clock. Within the digital system a transmit module transmits data along with a capture clock signal to a receive module where the transmission time between the modules is greater than one period of the system clock. The capture clock operates in a known relationship to the system clock at a frequency at least twice as slow as the system clock. The digital system also has a synchronizing clock that operates at the same frequency as the forwarded clock. When the data arrives at the receive module it is captured by a pair of memory devices operating on different phases of the capture clock. The memory devices feed the data to a multiplexor that selects, as a function of the synchronizing clock, between the outputs of the two memory devices.

Abstract: A memory device and method which provide at least one memory segment. The memory segment includes at least one first portion which is configured to store data. The memory segment also includes at least one second portion associated with the first portion, and which is configured to store directory information for at least one cache line thereon.

Abstract: A display is capable of displaying images in response to signals of a plurality of signal formats. The display includes a controller that is coupled to a plurality of image data interfaces. When the plurality of image data interfaces are simultaneously operating, the controller selects one of the plurality of image data interfaces according to preference variables associated with each of the plurality of image data interfaces. Each of the preference variables may indicate a relative priority of an image data signal format associated with the corresponding image data interface. In addition, each of the preference variables may indicate one or more performance metrics associated with the quality of image data signals received from the corresponding image data interface.

Abstract: A system and method for distributing data in a system. The system comprises a control register logic circuits located at scattered locations in the system, where a location is defined as scattered if the propagation delay of data sent from the control register is more than approximately one clock period. The system also comprises one or more shift registers coupled to the control register and the logic circuits. A section of each shift register is placed in proximity to each logic circuit and data is shifted serially from the control register through the shift registers to the logic circuits. A synchronizer circuit is coupled to the shift registers to synchronize data arriving at each section of the shift registers with a shift control signal arriving at the same section of the shift register.

Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem. In response to the failure of a node, a pre-defined order of procedures is attempted, executing one procedure at a time in the order defined, until successful completion of one of the procedures. Preferably the order is based on input from a system administrator, or a default order when no input has been provided by the system administrator. The procedures may include hardware reset of a failed node, disabling access by the failed node to the storage devices shared by the nodes in the cluster, terminating shared filesystem services on the failed node and terminating shared filesystem services on all of the nodes in the cluster.

Abstract: Apparatus and methods for reducing circuit board flexing is presented. The apparatus is fastened to a printed circuit board to provide rigid support for reducing bending and flexing. In one embodiment, a rigid frame is provided that is adapted to be fastened to one or more components and to be fastened to a printed circuit board. The frame is adapted to elevate the attached component from the PCB surface allowing components to be mounted on the PCB therewith. The frame is adapted to occupy minimal printed circuit board surface area so as not to displace electronic components. In another embodiment, an elongated truss-like stiffener is provided that is adapted to be fastened to one side of the printed circuit board and adapted to span the printed circuit board. The elongated stiffener is adapted to have an open structure to minimize cooling flow disturbance and weight. The elongated stiffener includes a plurality of legs forming a truss-like structure.

Abstract: A multithreaded layered-code processing method includes: passing through the layered code to discover each layer of the layered code, acquiring a lock when a layer is discovered, determining whether to spawn a thread to process the discovered layer, and, if it is so determined, spawning a thread to process the discovered layer. The method may further include: releasing the lock once the new thread is either spawned or aborted, and, if spawned, proceeding with execution of the thread concurrently with other threads. Other embodiments include a processor for carrying out the method and a computer-readable medium having stored thereon instructions to cause a computer to execute the method.

Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem. During relocation of a server for a distributed name service and recovery of a cluster, entries related to the distributed name service for filesystems is updated. During relocation, a new server for a filesystem informs all nodes in the cluster of the new server's location. During recovery, a process executing on each node deletes entries related to the distributed name service for any filesystem that does not have a server in the recovering cluster.

Abstract: The present invention is a system that provides a pen based computer user with a graphical user interface tool, a pen-mouse, that looks like and functions like a mouse but that is controlled by a limited input device such as a pen or stylus of the pen based computer. The pen-mouse is a tracking menu that tracks the position of the pen. A pen cursor that corresponds to the pen is allowed to be moved about within the pen-mouse graphic by the pen and the pen-mouse remains stationary. The pen-mouse is moved when the location of the pen encounters a tracking boundary of the pen-mouse. The tracking boundary typically coincides with the graphic representing the mouse. While moving within the pen-mouse, the pen can select objects within the pen-mouse body, such as buttons, wheels, etc. The selection of a button or other virtual control causes a corresponding computer mouse button function to be executed.

Abstract: The present invention is a system that provides a user with a pan-zoom tool that is controlled by a limited input device, such as a pen or stylus, of a pen based computer. The pan-zoom tool is a semitransparent, bull's eye type tracking menu that tracks the position of the pen. A pen-cursor or tracking symbol that corresponds to the location of the pen is allowed to move about within a pan-zoom tool graphic. The tool is moved when the location of the pen encounters a tracking boundary of the tool at an exterior edge of the menu. While moving within the pen-mouse the pen can select pan and zoom functions located in concentric rings of the tool graphic as the active function of the tool. Once one of the pan or zoom functions is activated motion of the pen on the surface of the display is interpreted as corresponding pan or zoom control commands, the tool is becomes transparent and the tracking symbol is replaced by a corresponding pan or zoom icon.

Abstract: A modular computing system that includes an enclosure with a rack. A plurality of modular bricks that each include heat-generating electronic components are mounted in the rack. A fan brick that includes at least one fan is also mounted in the rack. The fan brick exchanges air between each modular brick and the fan brick to cool the electronic components in each of the modular bricks.

Abstract: A method for exchanging messages between computer systems communicatively coupled in a computer system network. A message (e.g., a read or write command) is sent from a software element of a first computer system (e.g., a client computer system) to a second computer system (e.g., a server computer system). A shared memory unit is accessible by the software element of the first computer system and a software element of the second computer system. The shared memory unit of the second computer system is directly accessed, bypassing the processor of the second computer system, and the data of interest is read or written from/to the shared memory unit. In one embodiment, the method pertains to acknowledgments between software elements. A plurality of messages is sent from one software element to another software element. A count of each of the plurality of messages is maintained.

Abstract: A system and a method of scheduling a plurality of threads from a multi-threaded program. A shared arena is provided in user memory, wherein the shared arena includes a register save area for each of the plurality of threads. A processor, when allocated to the application, executes the application's user-level scheduler and selects a user-level thread from a plurality of available threads, wherein the step of selecting includes the step of reading register context associated with the selected thread from one of the plurality of register save areas. In multikernel systems, kernels having access to an application's register save areas can execute preempted threads from that application with no kernel-to-kernel communication. Likewise, kernels having access to an application's user-level run queues can execute ready-to-run threads from that application with no kernel-to-kernel communication.