Abstract: A method for creating a new subdivision surface from one or more prior subdivision surfaces using a computer, the computer having a processor and a memory, includes establishing in the memory a data structure storing data representing the structures of the prior subdivision surfaces, performing Boolean operations upon prior meshes defining the one or more prior subdivision surfaces to form a resulting mesh defining the new subdivision surface, and storing the resulting mesh in the memory.

Abstract: The present invention provides a method, a device, and a system for performing gamma correction on a set of pixel data based on a gamma correction curve table. The gamma correction curve table includes a specified total number of intensity levels associated with gamma corrected pixel values with one intensity level per pixel value. The method includes partitioning the gamma correction curve table into N segments such that each of the N segments is associated with a set of intensity levels from the specified total number of intensity levels. A plurality of intensity levels is selected for each of the N segments such that significant banding effects are not visible to the human eye between an adjacent pair of the selected intensity levels. The gamma corrected pixel values are stored for each of the N segments such that each of the plurality of selected intensity levels functions as an index to the associated gamma corrected pixel values.

Abstract: A method, system, and computer product uses a hashed static single assignment (SSA) form as a program representation and a medium for performing global scalar optimization. A compiler, after expressing the computer program in SSA form, can perform one or more static single assignment (SSA)-based, SSA-preserving global scalar optimization procedures on the SSA representation. Such a procedure modifies, (i.e., optimizes) the SSA representation of the program while preserving the utility of its embedded use-deprogram information for purposes of subsequent SSA-based, SSA-preserving global scalar optimizations. This saves the overhead expense of having to explicitly regenerate use-def program information for successive SSA-based, SSA-preserving global scalar optimizations.

Abstract: A data structure visualization tool visualizes a data structure such as a decision table classifier. A data file based on a data set of relational data is stored as a relational table, where each row represents an aggregate of all the records for each combination of values of the attributes used. Once loaded into memory, an inducer is used to construct a hierarchy of levels, called a decision table classifier, where each successive level in the hierarchy has two fewer attributes. Besides a column for each attribute, there is a column for the record count (or more generally, sum of record weights), and a column containing a vector of probabilities (each probability gives the proportion of records in each class). Finally, at the top-most level, a single row represents all the data. The decision table classifier is then passed to the visualization tool for display and the decision table classifier is visualized.

Abstract: An electrical connector (10) includes a cable dock (12) having a first connector (16) and a backshell assembly (14) having a second connector (18). The second connector (18) is adapted for engagement with the first connector (16). The electrical connector (10) also includes a locking element (40) coupled to the cable dock (12) and a latch (46) coupled to the backshell assembly (14). The latch (46) is operable to engage the locking element (40) and, in response to movement of the latch (46) relative to the backshell assembly (14), engage the first connector (16) with the second connector (18).

Abstract: A computer graphics system having a hyperpipe architecture. Multiple rendering pipes are coupled together through a hyperpipe network scheme. Each of the rendering pipes are capable of rendering primitives for an entire frame or portions thereof. This enables multiple rendering pipes to process graphics data at the same time. A controller coordinates the multiple rendering pipes by sending requests to the appropriate rendering pipes to retrieve the pixel data generated by that particular pipe. It then merges the pixel data received from the various rendering pipes. A single driver then draws the three-dimensional image out for display.

Abstract: A texture procedure allows the rendering of curve bounded objects to a graphics display device directly from a high level curve-based description. The method comprises receiving a curve-based description of the graphics object and dividing the graphics object into a rectangular mesh of texels. Each texel is then detailed by defining a combination of curved geometry functions and a boolean function. These function are then evaluated for each pixel of the graphics display device thereby rendering the graphics object to a graphics display. The texture procedure features include being procedural based and not image-based. This allows a rendering with continued accuracy even under arbitrary magnification conditions. Furthermore, the texture procedure is defined as such that will allow it to function using conventional tri-linear interpolation hardware.

Abstract: A memory management and control system that is selectable at the application level by an application programmer is provided. The memory management and control system is based on the use of policy modules. Policy modules are used to specify and control different aspects of memory operations in NUMA computer systems, including how memory is managed for processes running in NUMA computer systems. Preferably, each policy module comprises a plurality of methods that are used to control a variety of memory operations. Such memory operations typically include initial memory placement, memory page size, a migration policy, a replication policy and a paging policy. One method typically contained in policy modules is an initial placement policy. Placement policies may be based on two abstractions of physical memory nodes. These two abstractions are referred to herein as “Memory Locality Domains” (MLDs) and “Memory Locality Domain Sets” (MLDSETs).

Abstract: A system and method for providing power to the gates of a semiconductor chip routes power and ground from one layer of the chip to another layer of the chip using a first metal strip located at a first metal layer and a second metal strip located at a second metal layer, wherein the second metal layer is not directly adjacent to the first metal layer. A stacked via is used to connect the first metal strip to the second metal strip. The stacked via may comprise, for example, a first via connecting the first metal strip to an intermediate metal strip and a second via connecting the intermediate metal strip to the second metal strip. Alternatively, the stacked via may comprise a plurality of vias connecting the first metal strip to the intermediate metal strip and a plurality of vias connecting the intermediate metal strip to the second metal strip.

Abstract: The present invention is drawn to a system for attaching and supporting a cable to an IO panel of an electronic component such as the IO back panel of a computer. The system is comprised of a cable dock coupled to an IO panel, with a gasket disposed within the cable dock to form a conducting path from the IO panel to the cable backshell. In particular, a cable dock is fixed to the IO panel where an IO connector is exposed. Once the cable backshell is plugged into the cable dock, the cable dock provides mechanical support for a cable assembly comprising the cable-end connector, the cable backshell and the cable. The cable assembly is secured by the cable dock rather than by the coupling made between the cable-end connector and the IO connector. The cable dock also orients the cable-end connector in coupling to the IO connector such that the cable backshell is prevented from being incorrectly plugged into the cable dock.

Abstract: A matrix processor comprises a system with a variable number of buses, each bus having a variable number of processing elements which may operate in parallel. Each bus accesses a port into a memory crossbar and a multiport memory system also accesses crossbar ports. Efficient sharing of bus accesses by processors and synchronization of processors on each bus is accomplished via registers located on the buses, which may be read and written by processors. Interbus synchronization is also accomplished via register accesses. The matrix processor may be configured as a coprocessor or as a stand alone device. A method of synchronizing the processors and buses, performed by at least one processor on at least one bus, includes reading a barrier state of the processors, synchronizing the processing elements on a each bus, reading the barrier state of the buses, and synchronizing each bus.

Abstract: A switched router for transmitting packetized data concurrently between a plurality of devices coupled to the switched router. The devices are coupled to the I/O ports of the switched router. The switched router is then programmed to route packets of data from various source ports to several destination ports. Different packets may be transmitted concurrently through the switched router. The packets are comprised of a command word containing information corresponding to packet routing, data format, size, and transaction identification. Furthermore, the command word may include a destination identification number for routing the packet to a destination device, a source identification number used by a destination device to send back responses, a transaction number to tag requests that require a response, and a packet type value indicating a particular type of packet.

Abstract: A configurable synchronizer (10) for DDR-SDRAM (12) is provided that includes a strobe select module (40) operable to receive a memory select signal (106) and to pass strobe signals (20, 30) from one or more DDR-SDRAMs (16, 18) to a number of synchronizer circuits (44) corresponding to data signals (17) passed in parallel by each DDR-SDRAM as indicated by the memory select signal (106). A rising edge latch (174) receives a rising edge data signal (170) and latches the rising edge data signal (170) through the rising edge latch (174) on a rising edge of the strobe signal (152). A falling edge latch (176) receives a falling edge data signal (172) and latches the falling edge data signal (172) through the falling edge latch (176) on a falling edge of the strobe signal (152).

Abstract: A method, system and a computer program product for visualizing a decision-tree classifier are provided. The structure of a decision-tree classifier is mapped into a three-dimensional decision-tree visualization. The three-dimensional decision-tree visualization is displayed, representing the structure of the decision-tree classifier. Nodes in the three-dimensional decision-tree visualization include graphical objects representing nodes arranged in a hierarchy. The nodes in the three-dimensional decision-tree visualization correspond to nodes in the decision-tree classifier. Graphical attributes representative of information at corresponding nodes of the decision-tree classifier are provided at each node in the three-dimensional decision-tree visualization.

Abstract: A method of correlating a group of related processes residing on separate computers of a computer network so that they can be treated as a single entity. A single, large program is split up into separate processes and simultaneously run on several different computers. These related, but separate, processes are assigned a unique identifier. When a new process is created, it is assigned the same identifier as that of the process from which it was created, even though the child process might reside on a different computer. If a process determines that it should not belong to its current group, that process can create its own group by requesting that it be assigned a new identifier. Based on the identifiers, it is possible to implement programs that treat related processes as a single entity.

Abstract: The present invention provides a method and a device for generating texture coordinates for a selected pixel within a triangle for a texture wrapping operation. The selected pixel is defined within the triangle by a plurality of barycentric coordinates. The method includes receiving a set of texture coordinates for each of the vertices of the triangle and receiving a plurality of barycentric coordinates associated with the selected pixel. The method further includes determining a plurality of barycentric coefficients for the selected pixel from the texture coordinates of the vertices of the triangle. The barycentric coefficients are optimized to obtain a specified degree of precision, which is adapted to distinguish between neighboring texture coordinates. In addition, the method includes computing the texture coordinates based on the barycentric coefficients and the barycentric coordinates, wherein the texture coordinates are substantially distinct from neighboring texture coordinates.

Abstract: A media coprocessor for performing 3-D graphics, video, and audio functions. The media coprocessor is comprised of a single IC semiconductor chip which is coupled with a host processor chip, one or more memory chips, and an I/O controller chip. The media coprocessor includes a digital bitstream processor, a digital signal processor, and a display processor. An update interval, synchronized to a video frame, is defined. This update interval is divided into a number of partitions. Audio data is processed during one of the partitions. Video data is processed during another partition. And 3-D graphics is processed in another partition. Thereby, the processing is performed in a sequential, time-division multiplex scheme whereby the single media coprocessor chip processes all three partitions in a single video frame.

Abstract: A method of computer generation of a curve through points includes accepting positions of the points, accepting a geometric continuity condition for at least one of the points, constructing the curve through the points, the curve obeying the geometric continuity condition, and storing the constructed curve in a memory.

Abstract: A method and apparatus for volumetric three-dimensional fog rendering is provided. To add fog effects to an image, a host processor computes the location of the eye-point relative to the image to be fogged. Using the eye-point location, the host processor generates a three-dimensional fog texture and a blending function. The three-dimensional fog texture and blending function are downloaded or otherwise passed by the host processor to the graphics processor. The graphics processor then renders the primitives that make up the image. When rendering is complete, the graphics processor applies the tree-dimensional fog texture in an additional rendering pass. The method may then be repeated, to create animated fog effects such as swirling or wind-driven fog.