Patents Assigned to Silicon Graphics
  • Publication number: 20030006799
    Abstract: A driver operable with two power supplies, and provides, among other things, a high data communication rate, stabilized operating parameters including voltage output high, voltage output low, and on resistance, and edge rate over a wide range of variations in manufacturing process, operating voltages and temperature.
    Type: Application
    Filed: July 31, 2002
    Publication date: January 9, 2003
    Applicant: Silicon Graphics, Inc.
    Inventor: Rodney Ruesch
  • Patent number: 6496909
    Abstract: In a method for providing concurrent access to virtual memory data structures, a lock bit for locking a virtual page data structure is provided in a page table entry of a page table. The page table is configured to map virtual pages to physical pages. Then, a first thread specifying an operation on the virtual page data structure is received. The first thread is provided exclusive access to the virtual page data structure by setting the lock bit in the page table entry such that other threads are prevented from accessing the virtual page data structure. A wait bit also may be provided in the page table entry to indicate that one or more of the other threads are in a wait queue when the first thread has exclusive access to the data structure. When the first thread no longer needs exclusive access to the data structure, a second thread is selected from among the other threads and is provided with exclusive access to the data structure.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: December 17, 2002
    Assignee: Silicon Graphics, Inc.
    Inventor: Curt F. Schimmel
  • Patent number: 6496048
    Abstract: A system and method of controlling delay in a delay line. In a delay line having a system mode and an oscillator mode, wherein the delay line delays a signal as a function of a delay code, the method comprises setting the delay code, placing the delay line in oscillator mode, determining frequency of oscillation of the delay line, comparing the frequency of oscillation to a target frequency and adjusting the delay code until the frequency of oscillation of the delay line is substantially equal to the target frequency.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: December 17, 2002
    Assignee: Silicon Graphics, Inc.
    Inventor: Mark Ronald Sikkink
  • Patent number: 6496385
    Abstract: A printed circuit card carrier permits exchange of a card during continuous operation of electronic equipment, and thus without the need to remove an upper part of the enclosure to gain access to the card for upward removal from a motherboard connector. The carrier includes a movable printed circuit card holder that slides along the carrier, perpendicularly towards and away from the motherboard. An actuator accessible from outside the equipment and the holder are coupled together such that motion of the actuator is directed into perpendicular sliding motion of the holder. This either removes the printed circuit card from the motherboard connector or installs it into connector, depending on the direction of motion of the actuator. The carrier is particularly adapted for cards meeting the PCI standard.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: December 17, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: Stephen D. Smithson, Bruce Garrett, Roger Ramseier, Steve J. Dean, Paul Wiley
  • Patent number: 6493603
    Abstract: The invention described herein is a method, system, and computer program product for the design and fabrication of the surfaces of an object. The process begins by using a CAD process to design surfaces of the object. In particular, the surfaces are modeled using developable surfaces only. The intersections of the developable surfaces are then calculated. Any excess surface area of the developable surfaces is then trimmed. The boundaries of each developable surface are abstracted to produce a two-dimensional planar model of each developable surface. From each planar model, a full-sized two-dimensional shape can then be fabricated in proportion to the planar model. Each fabricated shape can then be bent in accordance with the corresponding developable surface of the CAD model. Finally, the edges of the fabricated shapes are attached as determined by the calculated intersections of the developable surfaces of the CAD model.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: December 10, 2002
    Assignee: Silicon Graphics, Inc.
    Inventor: Paul Haeberli
  • Publication number: 20020182925
    Abstract: A cable connector backshell assembly for high frequency applications requiring reduced electromagnetic emissions. Aspects include providing sufficient physical spacing and electrical isolation between the signal conductors and the housing to meet EMI standards for HIPPI-6400 connector assemblies. One embodiment includes spring preloading of the electrical connecter. One embodiment includes a longitudinally floating connector.
    Type: Application
    Filed: July 24, 2002
    Publication date: December 5, 2002
    Applicant: Silicon Graphics, Inc.
    Inventors: Duane Friesen, Val Mandrusov
  • Publication number: 20020175730
    Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 28, 2002
    Applicant: Silicon Graphics, Inc.
    Inventors: John F. DeRyckere, Philip Nord Jenkins, Frank Nolan Cornett
  • Publication number: 20020175728
    Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 28, 2002
    Applicant: Silicon Graphics, Inc.
    Inventors: John F. DeRyckere, Philip Nord Jenkins, Frank Nolan Cornett
  • Patent number: 6487685
    Abstract: A method for minimizing ECC bits in variable sized data formats is provided that comprises determining the number of ECC bits needed for each of a plurality of data formats and creating a common data representation for using a single implementation of error detection and correction logic for all of the plurality of data formats. The method then chooses an ECC matrix and default values for unused data bits in the common data representation such that any ECC bits beyond the minimum required for that sized data format will have known values thereby allowing smaller data formats to go through the error detection and correction logic using the common data representation. The method then retrieves a data entry having one of the plurality of data formats and formats the data entry into the common data representation.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: November 26, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: James A. Stuart Fiske, David E. McCracken
  • Patent number: 6486723
    Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: November 26, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: John F. DeRyckere, Philip Nord Jenkins, Frank Nolan Cornett
  • Patent number: 6487082
    Abstract: A printed circuit board apparatus, configurations and methods are presented which provide for close spacing between the HUB and multiple processors as well as a common configuration for two or four processor boards. A printed circuit board is provided with conductive apertures and portions corresponding to an efficient Packaging allowing for the attachment of the processor-chip on one side of the printed circuit board, and the HUB and other supporting electronic components on the other side of the printed circuit board. This configuration allows for the close spacing of the electrical conductors of the HUB and the processors without the limitations imposed by the physical dimensions of the respective hardware. Additionally, a symmetric packaging of the conductive apertures and portions about a centerline of the printed circuit board allows for a simple design modification to allow for a two two-processor board to be manufactured from a similarly configured four-processor board.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: November 26, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: Thomas Alex Crapisi, Jeffrey S. Conger, Stephen Cermak, III, Stephen A. Bowen, Rodney Ruesch, David Paul Gruber, Bonnie Kay Dobbs
  • Patent number: 6483024
    Abstract: A device for reducing electromagnetic interference (EMI) leakage through an opening in a housing. The device accepts a printed circuit board or dummy board. Various openings may be provided in the device. The device includes a faceplate, a gasket having a plurality of fingers, and a supporter. The supporter protects the leading edge of the fingers and augments the forces exerted by the fingers in opposition to the opening in the housing.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: November 19, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: Stephen D. Smithson, Steven J. Dean
  • Patent number: 6483699
    Abstract: An air cooled computer assembly including a printed circuit board assembly or a U sized enclosure. The computer assembly also includes three 120 mm fans positioned at one end of the PCB assembly providing air flow across the PCB assembly. The printed circuit board assembly has a top side and a bottom side, including heat producing components on the top side and bottom side. A portion of the heat producing components are DIMM memory positioned perpendicular to the direction of air flow. The computer assembly also includes an air baffling system positioned proximate to the PCB assembly. The air baffling system divides and balances the air flow between the heat producing components so that each of the components are adequately cooled. The air baffling system includes a flat baffle and pair of curved baffles. The flat baffle is positioned perpendicular to the direction of the air flow and is positioned between and in front of two 40 watt memory. The curved baffles are positioned adjacent to the two memory ASICs.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: November 19, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: Richard B. Salmonson, David Paul Gruber, Stephen A. Bowen
  • Patent number: 6480194
    Abstract: A computer graphics display method and system for controlling data visualization in at least one external dimension is provided which allows better querying and navigation of data in external dimension space. A data visualization is displayed in a first display window. A summary window provides summary information on data for the data visualization across one or more external dimensions. First and second controllers are displayed for controlling the variation of the data visualization in respective first and second external dimensions. A user queries the data visualization in the first and second external dimensions by selecting a point in the summary window. A user navigates through the data visualization in the first and second external dimensions by defining a path in the summary window. Grid points are also displayed in the summary window to facilitate data queries and navigation based on actual data points.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: November 12, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: Gerald P. Sang'udi, Ross A. Bott, Joel D. Tesler, John R. Hawkes, Rebecca W. Xiong, Mario Schkolnick
  • Patent number: 6480548
    Abstract: A method and apparatus for providing efficient and accurate electronic data transmission of information on a data bus in the presence of noise. Data signals are received on a plurality of input lines by a spacial derivative encoder. The spacial derivative encoder encodes the signals and transmits them to a receiver having a spacial derivative decoder. The spacial derivative decoder then decodes the signals. Minimal overhead is required as for n input lines only n+1 lines are needed to transmit each of the encoded signals.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: November 12, 2002
    Assignee: Silicon Graphics, Inc.
    Inventor: Daniel C. Mansur
  • Publication number: 20020163529
    Abstract: A system for color balancing within a liquid crystal flat panel display unit. The present invention includes a method and system for altering the brightness of two or more light sources, having differing color temperatures, thereby providing color balancing of a liquid crystal display (LCD) unit within a given color temperature range. The embodiments operate for both edge and backlighting systems. In an embodiment, two planar light pipes are positioned, a first over a second, with an air gap between. The first light pipe is optically coupled to receive light from a first light source having a color temperature above the predetermined range and the second light pipe is optically coupled to receive light from a second light source having a color temperature below the predetermined range.
    Type: Application
    Filed: December 13, 2001
    Publication date: November 7, 2002
    Applicant: SILICON GRAPHICS, INC.
    Inventor: Daniel E. Evanicky
  • Patent number: 6476813
    Abstract: A computer system (10) can prepare and present on a display (22) a two-dimensional image that includes a perspective view, from a selected eyepoint (71, 152), of an object (23) which is a three-dimensional object of an approximately spherical shape, such as the earth. The system maintains image information for the object at each of several different resolution levels, portions of which are selected and mapped into the perspective view for respective portions of the surface of the object. In order to determine what resolution level to use for a given section of the surface of the object, the system relies on a combination of a logarithm of the square of a distance from the eyepoint to a point on the surface section, and a logarithm of the square of the degree of tilt of the surface section in relation to the eyepoint.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: November 5, 2002
    Assignee: Silicon Graphics, Inc.
    Inventor: Paul Edward Hansen
  • Patent number: 6462740
    Abstract: A system for in-scene cloth modification that allows a user to make modifications to cloth during animation of objects associated with the cloth and have the new geometry updated in the in-scene cloth without having to start the animation from the beginning. Modified panels of the cloth are mapped into the counterpart panels of the simulated cloth by morphing the modified panels from a cloth definition into the space of the old panels in the scene. A relaxation of the cloth allows the new panel to take its natural shape in the animation. The mapping, when cloth is added, also includes finding each new panel vertex a location in the original or old panel.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: October 8, 2002
    Assignee: Silicon Graphics, Inc.
    Inventor: David Stanley Immel
  • Patent number: D464056
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: October 8, 2002
    Assignee: Silicon Graphics, Inc.
    Inventor: Charles W. Skandalis
  • Patent number: D464973
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: October 29, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: Philip J Houdek, Roger W. Ramseier, Stephen D. Smithson, Patrick J. Kurtz, Steven J. Dean