Abstract: A method, system, and computer program product visualizes the structure of an evidence classifier. An evidence inducer generates an evidence classifier based on a training set of labeled records. A mapping module generates visualization data files. An evidence visualization tool uses the visualization data files to display an evidence pane and/or a label probability pane. A first evidence pane display view shows a normalized conditional probability of each label value, for each attribute value. The first evidence pane display view can be a plurality of rows of pie charts. Each pie slice in a pie chart has a size which is a function of the normalized conditional probability of each label value for the respective attribute value. For each pie chart, the mapping module maps a height that is a function of the number of records in the training set associated with the evidence classifier.

Abstract: A node controller (12) includes a local block unit (28) that receives and processes request and reply packets. A request module (30) in the local block unit (28) receives a request packet and determines whether the request packet has an error. If there is no error, the request module (30) forwards local invalidation requests to a invalidation module (32) for processing and forwards programmed input/output read and write requests to a processor module (34) for processing. If an error is detected, the request module (30) forwards the request packet to a registers module (40). The registers module (40) stores the header and data contents of the request packet in header registers (70, 72) and a data register (80). An error bit is corresponding to the identified type of error is set in an error register (50). The request module (40) generates an interrupt signal (52) in response to setting the error bit in the error register (50).

Abstract: A method for controlling memory page migration in a parallel processor computer (10) is provided that comprises requesting access to a memory page (14) by a requester processor (206). The method then determines whether the requester processor (206) is a local processor or a remote processor. The method then increments a local access counter (52) and identifies the local access counter (52) as an incremented counter in response to determining that the requester processor (206) is a local processor. If the requester processor (206) is determined to be a remote processor, the method increments a remote access counter (54) and identifies the remote access counter (54) as the incremented counter. The method next sets a threshold processing indicator to a positive value if the incremented counter exceeds a value threshold (58) or if a difference between the local access counter (52) and the remote access counter (54) exceeds a difference threshold (62).

Abstract: A rack including a rail for supporting a computer module and a grounding element electrically coupled to the rack and positioned to electrically contact a computer module inserted in the rack such that the grounding element provides a path to ground. The grounding element can be an arcuate bracket attached to the rail to make contact with a side of the computer module. The grounding element can be a conductor extending from the rack and positioned to make contact with a side of the computer module. The rack can include a wider section which provides a cabling channel and a member on the rack for mechanically coupling the rack to an adjacent rack. The rack can include at least one passage for allowing a cable to pass through the rack to an adjacent rack and a cable organizer for maintaining placement of at least one cable routed through the passage.

Abstract: A multiple light source flat panel liquid crystal display (LCD) system having enhanced backlight brightness and specially selected light sources. According to the present invention, brightness in the LCD is enhanced by polarization recycling using a pre-polarizing film to pre-polarize light, and a special reflector for recycling light reflected by the pre-polarizing film. In one embodiment, the pre-polarizing film comprises a layer of DBEF brightness enhancement film, and the rear reflector is made of a PTFF material. In another embodiment, the rear reflector is covered with a film comprising barium sulfate. The multiple light sources are selected such that, at any color temperature within a predetermined range, the brightness of the LCD is not reduced below a given threshold minimum (e.g., 70 percent of the maximum brightness).

Abstract: A system and method of generating a clock signal as a function of a system clock. A plurality of overlapping phases are generated and two or more of the overlapping phases are combined to form the clock signal.

Abstract: A cable organizer having amounting mechanism suitable for mounting the cable organizer on a structure, at least one compartment for retaining at least one cable and a snap mechanism for use in installing the cable within the compartment.

Abstract: A heat sink assembly for securing a heat sink to a chip on a circuit board using a clip to secure the heat sink to the chip. The assembly includes a pair of support beams, a clip attached to the pair of support beams, and a heat sink. Optionally, the assembly also includes a plurality of bias members biased between the heat sink and the circuit board and a pair of positioning pins positioned between the heat sink and the circuit board. The clip is biased between the heat sink and the pair of support beams. The clip has a plate having a first end and a second end with the first end having an aperture for fastening the first end to a first support beam and the second end having a hook for fastening the second end to a second support beam. Optionally, the clip is made of spring steel and provides a downward biasing force of between about 3 psi and about 25 psi and preferably about 10 psi.

Abstract: A receiver operable with a single power supply provides, among other things, both differential and single ended signal detection with selectable noise margins. The output signals of differential amplifiers with hysteresis are coupled to logic gates. Internal test circuitry is also provided.

Abstract: A circuit board support operable with boards requiring a horizontal motion for engagement of connectors. The support can be exchanged for a traditional standoff and screw combination without modification of the board or supporting structure.

Abstract: A computer system (10) includes a node controller (12) operable to process invalidation requests. The node controller (12) includes a network interface unit (20), a memory directory interface unit (22), a processor interface unit (24), an input/output interface unit (26), a local buffer unit (28), and a crossbar unit (30). A local processor (16) generates an invalidation request that is processed by the processor interface unit (24) for placement into the local buffer unit (28). The invalidation request indicates that particular data within a local memory (18) associated with the node controller (12) has been altered by the local processor (16). The local buffer unit (28) generates a plurality of invalidation messages in response to the invalidation request, the invalidation messages being destined for remote processors (16) associated with remote node controllers (12) in the computer system (10) that share the particular data.

Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Abstract: A system and method for inexpensively detecting preempted execution entities such as threads without kernel involvement. In a computer system having a memory and one or more processors, a shared memory arena is formed in user space within the memory. A preempt bit vector is then formed within the shared memory arena such that the preempt bit vector is accessible to any of a plurality of execution entities running in user mode. The preempt bit vector includes a plurality of rbits, wherein each rbit is associated with one of the plurality of execution entities and wherein an rbit is marked whenever its associated execution entity is preempted. Detection of preempted threads then becomes a matter of reading, via program code executing in user mode on one of the plurality of processors, bits in the preempt bit vector to detect preempted execution entities.

Abstract: A system that includes a pop-up graphical user interface that includes menu bars overlapping marking menu zones. The interface pops up at the current position of the cursor when the space bar is held down. The menu bars are positioned around a central marking zone with the common menu bars located above the central zone and task specific menu bars located below the central zone. The common application menu bar is positioned outer most and the common window menu bar is located inner most. The menu bars are sized in a “stair-step” pattern and the commands therein are left and right justified to fill the menu bar evenly. The menu bar menu items are accessed just like menu bar items typically found at the top of windows. The menu bars mimic the menu bars that a user may need to use during tasks that users typically perform using the menu bars found in application windows.

Abstract: A system and method of cooling heat generating components. Heat generating components are placed in an enclosure having an air permeable cover. A mating panel having a mating connector is placed proximate to the air permeable cover. A fan assembly having a hub is coupled to the mating panel, wherein coupling includes wiring the fan to a fan connector, mounting the fan connector along an axial line running through the hub and pressing the fan assembly into the mating panel so as to mate the mating connector and the fan connector.

Abstract: A system and method are provided for automatically capturing a graphics session so that the session can be subsequently re-created in a precise manner. In some embodiments, the image data produced by the rendering process is recorded and stored in a memory medium. The image data can then be used to re-create the images produced by the original rendering process. The image data can be collected through a connection at the graphics processing host, at the client computer from which the graphics session is controlled, or at an intermediate point. In other embodiments, the initial state of the graphics processing host is captured, where the initial state includes the graphics data to be rendered. In addition, commands sent to the graphics processing host to control the graphics session are also captured. These commands are typically sent by the client computer from which the session is controlled.

Abstract: A bridge device (12) in a computer system interconnects with peripheral component interconnect (PCI) devices (14) over a PCI bus (16). The bridge device (12) includes a plurality of read response buffers (10) to provide data to the PCI devices (14). Each of the read response buffers (10) has a plurality of counters/registers (22) associated therewith. The counters/registers (22) measure various parameters associated with the request and retrieval of requested data and speculative data through the read response buffers (10). In response to the parameters measured by the counters/registers (22), the read response buffers (10) can be optimally allocated among the PCI devices (14).

Abstract: A computing device (12) includes a first process (16) and a second process (18) executing thereon in conjunction with a local memory (20). The local memory (20) stores data files retrieved from a database (14). The database (14) maintains the data files in page formats. Each page (22) maintained within the database (14) includes a counter location (24). The first process (16), desiring to write access a particular page (22), increments the counter location (24). The counter location (24) provides an indication that the contents of the particular page (22) are not valid. The second process (18), desiring to read or write access the particular page (22), determines that the particular page (22) is not in a valid state according to the counter location (24). The first process (16), upon terminating write access to the particular page (22), increments the counter location (24). The counter location (24) now provides an indication that the contents of the particular page (22) are in a valid state.