Patents Assigned to Silicon Graphics
  • Patent number: 5877767
    Abstract: A system and computer-based method for permitting a computer system to access a network location using a browser application by activating a desktop icon. The system comprises a first computer readable program code means for causing the computer system to display a desktop icon associated with a file containing a network address corresponding to the network location. When the desktop icon is activated, a second computer usable program code means causes the computer to launch an instance of a browser application or a new window for a currently executing browser application and a third computer usable program code means causes the computer system to pass the network address to the browser application, thereby accessing the network location.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: March 2, 1999
    Assignee: Silicon Graphics, Inc.
    Inventor: Steven J. Yohanan
  • Patent number: 5875468
    Abstract: In a computer system having a number of nodes, wherein one of the nodes has a number of processors which share a single cache, a method of providing release consistent memory coherency. Initially, a write stream is divided into separate intervals or epochs at each cache, delineated by processor synch operations. When a write miss is detected, a counter corresponding to the current epoch is incremented. When the write miss globally completes, the same epoch counter is decremented. Synch operations issued to the cache stall the issuing processor until all epochs up to and including the epoch that the synch ended have no misses outstanding. Write cache misses complete from the standpoint of the cache when ownership and data are present. This allows the latency of writes operations to be partially hidden in any combination of shared cache (both hardware and software controlled), and multiple context processors.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: February 23, 1999
    Assignee: Silicon Graphics, Inc.
    Inventors: Andrew Erlichson, Neal T. Nuckolls, Gregory L. Chesson
  • Patent number: 5872963
    Abstract: A system and method for context switching between a first and a second execution entity (such as a thread) without having to enter into protected kernel mode. The system includes a memory and a plurality of processors, wherein each of the plurality of processors operates within both a user mode and a protected kernel mode and includes a program counter and a plurality N of registers. The first and second execution entities have user states defined by a program counter value, a context identifier value and N register values. To switch context, an execution entity such as a thread, while in user mode, writes the user state of the first execution entity to memory. It then restores the user state of the second execution entity by writing register values associated with the second execution entity to all but a first register and writing the context identifier value to a context identifier location.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: February 16, 1999
    Assignee: Silicon Graphics, Inc.
    Inventors: Nawaf K. Bitar, Robert M. English, Rajagopal Ananthanarayanan, Alexander D. Petruncola, David Craig
  • Patent number: 5870574
    Abstract: A system and method for fetching instructions for use in a RISC processor having an on-chip instruction cache is disclosed. The system accesses a first group of instructions having a first set of ordered addresses and a second group of instructions having a second set of ordered addresses, simultaneously, from an instruction cache. The first group of instructions is to be executed during a first cycle and the second group of instructions is to be executed during a second cycle. The technique transfers the first group of instructions to an instruction decoder for execution during the first cycle and transfers the second group of instructions to the instruction decoder for execution during the second cycle. The technique reduces the power consumed by memory modules and support circuitry of the instruction cache by requiring instruction cache accesses only every other cycle.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: February 9, 1999
    Assignee: Silicon Graphics, Inc.
    Inventors: Andre Kowalczyk, Givargis G. Kaldani
  • Patent number: 5870325
    Abstract: A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: February 9, 1999
    Assignee: Silicon Graphics, Inc.
    Inventors: Michael J. K. Nielsen, Brian Kindle, Linda S. Gardner, Zahid S. Hussain
  • Patent number: 5867419
    Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: February 2, 1999
    Assignee: Silicon Graphics, Inc.
    Inventors: David P. Chengson, William L. Schmidt, Unmesh Agarwala, Alan D. Foster, Edward C. Priest, John C. Manton, Ali Mira
  • Patent number: 5867163
    Abstract: A method, apparatus and display for controlling defining and automatically executing a sequence of commands of a tool shelf. The user places (drags and drops) desktop icons from a tool box into a sequence tool shelf in an order in which the commands are to be executed. A directed list of the commands created during the placement of the icons in the sequence shelf, along with a current command pointer, is used to automatically control the execution of the commands in the order specified by the user. The execution can be performed without user input to indicate that the next command in the sequence should be executed or the user can control next command execution using a selection tool such as a marking menu. The icons of the commands are highlighted as the commands are executed to provide the user visual feed back concerning which command is currently being executed.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: February 2, 1999
    Assignee: Silicon Graphics, Inc.
    Inventor: Gordon P. Kurtenbach
  • Patent number: 5861891
    Abstract: A method, system, and computer program product are provided for visually approximating a scatter plot. Bins of scattered data points are formed. Each axis of a scatter plot is discretized according to a binning resolution. Bin positions along each discretized scatter plot axis are determined from the bin numbers. The bins, which represent a cloud of scattered data points, are volume rendered as splats. The opacity of each splat is a function of the number (count) of data points in a corresponding bin. In one example, the opacity of a splat is determined by the following equation:opacity=1-exp.sup.(-u*count),where count is the number of scattered data points in a corresponding bin, u is a global scale factor which can be varied by a slider, and exp is an exponential function. The color of the splat represents a data attribute associated with the data points in a corresponding bin.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: January 19, 1999
    Assignee: Silicon Graphics, Inc.
    Inventor: Barry Glenn Becker
  • Patent number: 5861815
    Abstract: A light bar and reflector assembly for indicating the status of a computing device is disclosed. A reflector assembly having a light source is connected to the chassis of a computer. The reflector assembly includes reflective surfaces that reflect light from the light source through an opening in the reflector assembly. A light bar is attached to the bezel such that, when the bezel is placed over the computer chassis, the light bar aligns with the opening in the reflector assembly. The light bar includes reflective surfaces so as to channel the light from the light source to refractive surfaces which refract the light into the air such that a distinctive light pattern is visible across the length of the light bar. The design of the light bar produces an intense broad band of visible light on the light bar. The light intensity dissipates towards each end of the light bar.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: January 19, 1999
    Assignee: Silicon Graphics, Inc.
    Inventor: Glenn Alan Wernig
  • Patent number: 5861885
    Abstract: A method and apparatus are presented for displaying a three-dimensional navigable display space containing an aggregation of graphical objects and an overview of the aggregation of display objects. An altered perspective is provided by compressing the horizontal dimension of the displayed objects so that a user can see a representative overview of the entire aggregation of display objects that have been selected for display together on a display screen. The compressed component is expanded so that the objects appear wider as a navigator approaches the displayed objects. A spotlight shines down on objects responsive to a data query. The spotlight serves as a navigation aid to the navigator so that highlighted items are visible from a distance and can be easily located.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: January 19, 1999
    Assignee: Silicon Graphics, Inc.
    Inventors: Steven Larry Strasnick, Joel Dave Tesler
  • Patent number: 5854631
    Abstract: A system and method for merging received pixel fragments with an existing fragment compares a depth range for the received fragment with a depth range for the existing fragment. If there is a range overlap, the new fragment is merged with the existing fragment for which there is overlap. If there is no range overlap, the new fragment is discarded. The merge operation can be performed for fragments received for a single surface, such as the nearest surface. Alternatively, the merge operation can be performed for fragments received for a plurality of surfaces.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: December 29, 1998
    Assignee: Silicon Graphics, Inc.
    Inventors: Kurt Barton Akeley, Carroll Philip Gossett
  • Patent number: 5848906
    Abstract: A loading and placement device for connecting circuit boards using a flex circuit and a compression connector is disclosed. A mounting mechanism holds one or more circuit boards and a flex circuit and a compression connector couple the circuit boards to a circuit board having a backplate hook and rail housings mounted onto it. The rail housings engage the frame of the mounting mechanism for easy alignment and secure attachment. A plate of the mounting mechanism slides so to engage and rotate a cam handle. The movement of the cam handle compresses the connector against the surface to which the backplate hook is mounted, thus achieving a positive connection which locks the compression connector into a position of uniform compression. The circuit boards may be disengaged by sliding the plate of the mounting mechanism so as to rotate the cams into the unlocked position and pulling the mounting mechanism out of the rail housings.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: December 15, 1998
    Assignee: Silicon Graphics, Inc.
    Inventors: Mark J. Glusker, David J. Lima
  • Patent number: 5848275
    Abstract: In a computer system having a cache memory and a main memory for storing data, a method for laying out blocks of data to minimize a number of memory transfers between the cache memory and the main memory. Memory layout normally occurs at link time, after all the source files have been compiled. The code is compiled with the assumption that the memory blocks can be optimally placed. The linker then determines whether there has been any memory violations. Memory violations are marked. All marked memory locations are then placed in a layout that satisfies adjacency requirements.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: December 8, 1998
    Assignee: Silicon Graphics, Inc.
    Inventors: Dror E. Maydan, Sun C. Chan, James C. Dehnert, Jack C. Carter
  • Patent number: 5847700
    Abstract: A circuit for translating pixel data to be displayed on the output display of a computer system including a plurality of color index maps for providing a first set of digital values of shades to produce a final color on an output display in response to color index values; and a plurality of gamma correction maps for providing a second set of digital values of shades to produce a final color on an output display in response to the first set of digital values of shades.
    Type: Grant
    Filed: August 10, 1993
    Date of Patent: December 8, 1998
    Assignee: Silicon Graphics, Inc.
    Inventor: Marc R. Hannah
  • Patent number: 5847716
    Abstract: A graphic structure having joint angles is manipulated from an initial configuration towards a goal configuration by a succession of iterations, in each of which an update configuration is derived from a prior configuration. A regular iteration determines at least one test configuration by modifying fewer than all of the joint angles of the prior configuration, determines, for each test configuration, an improvement value reflecting the improvement between the differences of the prior configuration and the test configuration with respect to the goal configuration, and selects a test configuration as the updated configuration based on the improvement values.
    Type: Grant
    Filed: July 31, 1996
    Date of Patent: December 8, 1998
    Assignee: Silicon Graphics, Inc.
    Inventor: Roy Hashimoto
  • Patent number: 5845874
    Abstract: A system and method for creating visual images of aircraft wake vortices allows a user, such as an aircraft controller, to increase a number of airport transactions while maintaining a predetermined level of safety. Wake vortices are simulated in a three dimensional environment taking into account various aircraft, environmental, and atmospherical conditions. The simulated wake vortices are rendered from a perspective selectable by the user. The displayed image allows the user to direct aircraft around potentially harmful wake vortices.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: December 8, 1998
    Assignee: Silicon Graphics, Inc.
    Inventor: Graham D. Beasley
  • Patent number: 5844567
    Abstract: Texture mapping using triangular interpolation in a computer graphics system is discussed herein. A texture mapping module maps a pixel from an image space to a sample point in a texture space. The sample point has coordinates (si+sf, ti+tf). The texture mapping module identifies the three texels in the texture space that form a triangular region enclosing the sample point. The texture mapping module determines whether the triangular region represents a lower region or an upper region.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: December 1, 1998
    Assignee: Silicon Graphics, Inc.
    Inventors: Carroll Philip Gossett, Robert J. Moore
  • Patent number: 5838921
    Abstract: A distributed connection management system for an interactive multimedia network that controls the allocation and recovery of bandwidth resources in the network between client and server. The connection manager accepts as input the topology of a network to be controlled and partitions the local access portion of the network into separately administered neighborhoods. Resources for each of the partitioned neighborhoods are allocated by a replicated neighborhood connection manager. The remainder of the network is partitioned into the switched ATM network and into server network resources. Resources within the switched ATM network are administered by an ATM connection manager. Resources into and out of the servers are managed using a server connection manager.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: November 17, 1998
    Assignee: Silicon Graphics, Inc.
    Inventor: Thomas H. Speeter
  • Patent number: 5834705
    Abstract: An apparatus for modifying a printed circuit board comprised of a nonconductively adhering flexible circuitized substrate, the flexible circuitized substrate having a conductive circuit trace composed of one or more layers of thin wires sandwiched between two or more layers of flexible insulating protective material. The wires forming the circuit trace of the flexible substrate and the conductors forming the circuitry in and on the printed circuit board are electrically interconnected at appropriate predetermined positions by establishing conductive paths through portions of the insulating layers of the flexible circuitized substrate. Circuit components can also be affixed to either the flexible circuitized substrate or to the printed circuit board or to both after the flexible circuitized substrate has been affixed to the printed circuit board.
    Type: Grant
    Filed: March 4, 1994
    Date of Patent: November 10, 1998
    Assignee: Silicon Graphics, Inc.
    Inventor: Siamak Jonaidi
  • Patent number: 5835717
    Abstract: A computer-based system and method for saving and restoring states in an interactive television system. The system presents interactive programs to a user; each program includes one or more states. When a user leaves a state in an interactive program by selecting a second state, the system saves state information sufficient to restore the first state. When the user elects to return to the first state, the system retrieves the state information and uses it to restore the first state; if the first state is not in the same interactive program as the second state, the system terminates the second state's interactive program and launches the first state's interactive program.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: November 10, 1998
    Assignee: Silicon Graphics, Inc.
    Inventors: Philip L. Karlton, Robert K. Myers