Abstract: A performance or show production system and method allows a performer to control and interact with an on-stage display or screen. The on-stage screen is used to create a virtual extension of the stage. Images displayed on the screen may include video playback and real-time generated, texture mapped graphics. The system includes a media production system for producing visual images, a display system for displaying the visual images, a tracking system for tracking the position of the performer on the stage and for producing a position indication, and a control system for controlling the production of visual images by the media system as a function of the position of the entertainer on the stage.

Abstract: A multiprocessor computer system and method for maintaining coherency between virtual-to-physical memory translations of multiple requestors in the system. A poison bit is associated with a memory block in the system. The poison bit is set to indicate that a virtual-to-physical memory translation for the memory block is stale. An exception is generated in response to an access by one of the requestors to the memory block if the poison bit is set, thereby indicating to the requestor that the virtual-to-physical memory translation entry for the memory block is stale. The virtual-to-physical memory translation for the memory block is then updated with a virtual memory translation corresponding to a new physical location for the memory block. In an embodiment having a cache-based multiprocessor system, the method further comprises the step of invalidating all cached copies of the memory block. In this case, the invalidating step and the setting step must be performed as an atomic operation.

Abstract: A system and method for facilitating communication between layers in a multi-layer system. Opaque information is utilized to pass information between layers in an indirect communication. A single horizontal communication between the highest layer in a first communication end of the system passes opaque information collected from all lower layers to the highest layer in a second communication end. Vertical communications are utilized to distribute the opaque information to the intended layer.

Abstract: The present invention discloses a novel arbitration procedure for selecting among devices in a computer system requesting access to a single resource such as, for example, a system bus or main memory. The arbitration procedure provides an efficient means for guaranteeing the available system bus bandwidth to devices having high bandwidth requirements. Each device can be allotted a certain amount of bandwidth that is guaranteed to be available for that device within a given time interval. Excess bandwidth not consumed by the guaranteed allotments can be used as remainder (e.g., available but not guaranteed) bandwidth by the devices. The arbitration procedure further provides a guaranteed maximum latency so that no device is prevented from completing data transfers in a timely manner. The arbitration procedure still further provides the ability to dynamically program the amount of the bandwidth that is guaranteed a particular device.

Abstract: The present invention provides a system and method for implementing interprocedural analysis using a standard compilation user interface. The present invention stores an intermediate representation of the source code, associated interprocedural summary information, and compilation options into an extended object format file. Interprocedural analysis functions are then performed on each of the extended object format files, resulting in IPA output files which preserve the compilation options. A compiler back end is invoked for each IPA output file to produce a standard format binary object file. The standard format binary object files are finally linked together to produce a final output, such that the final output can be either an executable program or a dynamic shared object. The present invention executes the interprocedural analysis functions, the compiler back end, and the linking under the control of a linkage editor.

Abstract: A method for simulating and rendering hair. A simulator calculates the motion dynamics of a hair. The simulator includes a particle system that emits particles from a surface and a normalization module that normalizes the trajectory of each of the particles to a fixed length to form a set of normalized segments. The simulator outputs a list of normalized segments that are passed to a renderer. The renderer performs a variety of tasks, including fuzzy segment generation and self-shadowing, that results in an image being displayed on a display device. That is, the renderer takes three-dimensional spacial information, applies a light to this information and renders this information as a two-dimensional image.

Abstract: A system and method are provided for displaying a uniform network resource locator embedded in a time-based medium. In one embodiment, the time-based medium can be a movie file having an uniform network resource locator embedded by association with a track in the movie file. In another embodiment, the time-based medium can be a video signal having encoded information defining an embedded uniform network resource locator. An output for display is generated based upon the time-based medium where display of the output shows the embedded uniform network resource locator to a user such that the embedded uniform network resource locator is active during display of the output. The user is then allowed to activate the embedded uniform network resource locator. In response to activation by the user, the embedded uniform network resource locator is followed to retrieve a resource addressed by the embedded uniform network resource locator.

Abstract: In a computer system having a cpu, a device for dynamic cpu clock adjustment. The device is comprised of a clock pulse generator for generating a clock frequency. The clock frequency is coupled to the cpu and is used by the cpu to synchronize and pace its internal operations. The clock frequency generated by the generator is variable over a range. A controller is coupled to the clock pulse generator, for adjusting the clock frequency from the clock pulse generator over the range. The controller interfaces with the computer system through an interface coupled to the controller. Through the interface, the controller communicates with the computer system or cpu and determines a load placed on the cpu. The controller adjusts the clock frequency generated by the clock pulse generator such that the clock frequency increases when the load on the cpu increases and the clock frequency decreases when the load on the cpu decreases, dynamically adjusting the clock frequency in response to the load on the cpu.

Abstract: An EMI bulk head gasket assembly includes a bulk head and a gasket adapted to snap fit together. The bulk head includes a base plate and first and second bulk head side walls, positioned at right angles to the bulk head base plate. The first bulk head side wall includes a plurality of bulk head apertures. The gasket includes a base plate and first and second gasket side walls wherein the first gasket side wall forms an angle slightly greater than ninety degrees with the gasket base plate. The gasket is adapted to snap fit between the first and second bulk head side walls. The first gasket side wall includes inwardly pointing tabs positioned and adapted to fit into the plurality of bulk head apertures. The tabs retain the gasket between the first and second bulk head side walls. The gasket includes spring fingers each of which include a spring bend between a proximal spring finger section and a distal spring finger section. The spring finger is spring loaded by the spring bend.

Abstract: A means and method is disclosed for displaying an image on a display screen graphically representing the topology and information transfer activity occurring on a computer network. One host computer on the network denoted a network monitor gathers information about the topology and traffic on the network. A display image is generated depicting a substantially circular arrangement of host computers and/or sub-networks of host computers comprising the network. Color-coded, dashed, various width, or shaded line segments are added to the display image representing traffic (information transfer activity) occurring on the network between source and destination host computers. Line segments between communicating hosts are coded depending upon the volume of information being transferred. Line segments are removed when information flow between a pair of hosts ceases. Controls are provided to configure the display of the network and to move or zoom in on a portion of the display image.

Abstract: This relates to a general purpose circuit that maximizes the computing power of a Unix workstation or other computer system for processing image or other data in accordance with a selected one or ones of several alternative compression and decompression algorithms. This dynamically allocates system memory for storage of both compressed and uncompressed data and ensures adequate compression and decompression rates.

Abstract: A system and method for transmitting data, using a source synchronous clocking scheme, over a communication (or data) link. A source synchronous driver (SSD) receives a micropacket of parallel data and serializes this data for transfer over the communication link. The serial data is transferred onto the communication link at a rate four times as fast as the parallel data is received by the SSD. A pair of source synchronous clocks are also transmitted across the communication link along with the serial data. The pair of clocks are the true complement of one another. A source synchronous receiver (SSR) receives the serial data and latches it into a first set of registers using the source synchronous clocks. The serial data is then latched into a second set of registers in parallel. The second set of registers are referred to as "ping-pong" registers. The ping-pong registers store the deserialized data.

Abstract: A system and method for an optimizer of a compilation suite for representing aliases and indirect memory operations in static single assignment (SSA) during compilation of a program having one or more basic blocks of source code. The optimizer converts all scalar variables of said program to SSA form, wherein said SSA form includes a plurality of variable versions, zero or more occurrences of a .chi. function, zero or more occurences of a .phi. function, and zero or more occurrences of a .mu. function. The .chi. function, .phi. function, and .mu. function are inserted for the variable versions. The optimizer also determines whether a variable version can be renamed to a zero version, and upon such a determination, the optimizer renames the variable version to a zero version.

Abstract: A synchronization backbone for use in a computer system having a system board containing at least one central processing unit for processing digital data, a memory coupled to the system board for storing the digital data, a plurality of subsystems, and a bus structure for transmitting electrical signals between the system board, the memory, and the plurality of subsystems. The synchronization backbone provides the infrastructure that enables professional quality synchronization between the various subsystems. A clock generator is used to generate a system clock that is transmitted to each of the subsystems. The sample rate of a designated subsystem is used as a digital synchronization signal. The selected digital synchronization signal is then transmitted to each of the other subsystems. A synchronization circuit adjusts the sample rates associated with the other subsystems according to the digital synchronization signal and the system clock.

Abstract: A method for simulating and rendering hair. A simulator calculates the motion dynamics of a hair. The simulator includes a particle system that emits particles from a surface and a normalization module that normalizes the trajectory of each of the particles to a fixed length to form a set of normalized segments. The simulator outputs a list of normalized segments that are passed to a renderer. The renderer performs a variety of tasks, including fuzzy segment generation and self-shadowing, that results in an image being displayed on a display device. That is, the renderer takes three-dimensional spacial information, applies a light to this information and renders this information as a two-dimensional image.

Abstract: An apparatus and method for quickly and efficiently providing texel data relevant for displaying a textured image. A large amount of texture source data, such as photographic terrain texture, is stored as a two-dimensional or three-dimensional texture MIP-map on one or more mass storage devices. Only a relatively small clip-map representing selected portions of the complete texture MIP-map is loaded into faster, more expensive memory. These selected texture MIP-map portions forming the clip-map consist of tiles which contain those texel values at each respective level of detail that are most likely to be mapped to pixels being rendered for display based upon the viewer's eyepoint and field of view. To efficiently update the clip-map in real-time, texel data is loaded and discarded from the edges of tiles.

Abstract: A system and procedure for placement optimization of input/output ports associated with edges of circuit blocks within an integrated circuit design. The integrated circuit design is composed of circuit blocks that communicate using inter-block signal wires coupled to input/output ports (IOPs) located along edges of circuit blocks. An arbitrary IOP placement is first received, e.g., from a global floorplanner, and indicates (1) the allowable edge placement domains for each IOP and can optionally include (2) an arbitrary IOP placement within these allowable edge domains. A cell placer (e.g., a quadratic based standard cell placer) receives the arbitrary IOP placement and, for each circuit block, places cells represented within internal netlists. The placer does not optimize the placement of the IOPs. For each IOP, the set of cells of the net that is coupled to the IOP is determined.

Abstract: Redundant mapping tables for use in processors that rename registers and perform branch prediction is presented. The redundant mapping tables include a plurality of primary RAM cells coupled to a plurality of redundant RAM cells. In the event of a branch instruction, the redundant RAM cells can save the contents of the primary RAM cells in a single clock cycle before the processor decodes and executes subsequent instructions along a predicted branch path. Should the branch instruction be mispredicted, the redundant cells can restore the primary RAM cells in a single clock cycle. A branch stack, coupled to the redundant mapping tables, updates restored mapping tables with changes made for preceding instructions that were decoded in parallel with the branch instruction. A plurality of levels of redundant RAM cells may be used to enable the nesting of a plurality of branch predictions at any one time.

Abstract: An indexing method allows a viewer to control the mode of delivery of program material while minimizing the time offset between audio and video data so that the viewer does not perceive a time delay between the audio and video. Video data frames may be grouped together into units referred to as "Groups of Pictures" (GOP's) comprising one or more frames. Synchronization is performed by correlating audio frames of the audio data with GOP's of the video data. When jumping to various points in an item of program material, this indexing method ensures that a jump is made to the beginning of a GOP. To prevent audio data from being "out of sync", the audio data must be correlated with the corresponding GOP. To do so, an index file for the video data is constructed, and then the video data index file is used to construct an index file for the corresponding audio data.