Abstract: A circuit is described for providing switching between two asynchronous clocking signals in a graphics generation apparatus. In transitioning from one clocking signal to the other, the ending clocking signal ends at the end of a complete cycle, and the beginning clocking signal begins at the beginning of a new cycle. There is dead time between the clocking signals long enough to prevent transients which could disturb the operation of the system. The clocking signals are used to control data transfers of a graphics processor within the graphics generation apparatus.

Abstract: A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.

Abstract: A method and apparatus for producing a visually improved image on a video display in a computer controlled display system. The system and method converts a quadrilateral polygon to a pair of triangles by computing the dot product of the normal unit vectors of one set of opposing pair of vectices and computing the dot product of the normal unit vectors of the other set of opposing pair of vertices and then comparing these two dot products to determine which opposing pair of vertices produces the larger of the two dot products. The pair of opposing vertices which produces the largest dot product is used to form the common edge of the pair of triangles into which the quadrilateral is converted.

Abstract: A method and apparatus for painting in a computer controlled video display system is described. A current shape of a brush stroke is determined. A current direction of the brush stroke is determined. A current position is determined. A current color is set equal to a color at the current position. The step of drawing the brush image on the display comprises the steps of setting a color of the brush image equal to the current color, setting a position of the brush image equal to the current position, and setting a direction of the brush image equal to the current direction of the brush stroke.

Abstract: A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.

Abstract: A graphics processor is coupled to a plurality of RAMs (Random Access Memories) for storing a frame of a display. The processor provides a separate RAS (Row Address Strobe) signal and a separate CAS (Column Address Strobe) signal to each of the memories so that row and/or column addresses to each of the RAMs can be latched using a staggered timing sequence. Data can be written into or read from memory using this staggering technique, wherein overall data transfer rate is faster than the memory cycle time of each to of the RAMs.

Abstract: A method for forming a computer model of a modified bounded volume representing a portion of a bounded volume on a cutting surface and to a first side of the cutting surface. After signed distances are calculated, either (1) the first face is modified by deleting the first edge from the first face of the bounded volume, (2) the first edge on the first face is retained, or (3) the first edge of the first face is modified by interpolation. The above steps are repeated for each of the remaining edges of the bounded volume. If the first face has been modified and is missing an edge, then (1) a first cut-face edge is generated for the first face, (2) the first cut face is stored, and (3) the first face is modified by adding the first cut-face edge to the first face. If the first face has been modified, then the first face is stored as modified. Otherwise, the unmodified face is stored. The above steps following the generation of the list of edges is repeated for each of the remaining faces of the bounded volume.

Abstract: A system for displaying graphic images comprising an arrangement for clipping polygons against preselected clipping planes, an arrangement for determining when the vertices of a polygon all lie within one of a number of particular subspaces defined by the clipping planes, and an arrangement for disabling the means for clipping so long as all vertices of a polygon lie in the same subspace.

Abstract: A method and apparatus for clearing a Z-buffer in a raster scanned, computer controlled video display system having a frame buffer and a Z-buffer is disclosed. The method includes the step of writing a plurality of bits into pixel locations of the frame buffer, which pixel locations will be cleared in the Z-buffer and on the screen of the video display. Those plurality of bits invalidating the Z values in the Z-buffer corresponding to those pixel locations.

Abstract: A graphics processor is coupled to a plurality of RAMs (Random Access Memories) for storing a frame of a display. The processor provides a separate RAS (Row Address Strobe) signal and a separate CAS (Column Address Strobe) signal to each of the memories so that row and/or column addresses to each of the RAMs can be latched using a staggered timing sequence. Data can be written into or read from memory using this staggering technique, wherein overall data transfer rate is faster than the memory cycle time of each of the RAMs.

Abstract: The present invention is a device for the easy installation and removal of a drive system from a computer housing. The invention also comprises a novel release button designed to activate the release mode of the drive system, and is also generally useful as a button assembly.

Abstract: A method for updating a single ported, pipelined Z-buffer where the Z-buffer is updated only after determining the beginning and ending location of a continuous group of pixel locations requiring updating in the Z-buffer.

Abstract: A system for processing of data wherein the data is inputted over time into the system such that a second packet of data is inputted before a first packet of data, the system comprising a first processor coupled to a second processor, the first processor operating on only the first packet of data and the second processor operating on only the second packet of data.

Abstract: An improvement for providing color information in a raster scanned video display apparatus where color data is stored in a frame buffer for each pixel in addition to color data. The color data is coupled to a crossbar switch to provide several sets of color data at the output of the switch. A multiplexer receives these several sets of color information and selects between them based on the color mode data. This permits the same color code to represent more than a single color. In a display, color in windows may then be generated from different programs, eliminating color-code dependencies between programs.

Abstract: YA dual clock shift register for use in a computer display system for converting a higher resolution image for a computer screen to a lower resolution image for display on a lower resolution display apparatus. The dual clock shift register includes a first shift register which is used to apportion a second shift register between control by two different clock rates.