Abstract: A loop scheduler in a software compiler system for generating a schedule for executing in a target computer loops of instructions contained in a computer program is described. The loop scheduler operates by searching for an optimal loop schedule for executing a particular instruction loop in the target computer. The loop scheduler then identifies loop overhead instructions and non-loop overhead instructions in the particular instruction loop. A replicated loop schedule is generated by the loop scheduler by replicating the non-loop overhead instructions in the loop schedule by a replication factor such that overlap of each operation instance in the optimal loop schedule with itself is prevented. The loop scheduler inserts the loop overhead instructions into the replicated loop schedule to generate a modified loop schedule, and then allocates registers of the target computer to the modified loop schedule.

Abstract: A system and method of interactively generating computer graphic images for incorporating three dimensional textures. The method of the present invention includes defining an orientation of a polygon relative to a plurality of three dimensional (3D) texture data sets, determining a level of detail of a pixel associated with the polygon, and selecting a first 3D texture data set and a second 3D texture data set from the plurality of 3D texture data sets in accordance with the pixel level of detail. The method also includes mapping the pixel to a first position within the first 3D texture data set and to a second position within the second 3D texture data set in accordance with the orientation, and generating a display value for the pixel in accordance with the mapping of the pixel to the first and second positions.

Abstract: A cache memory system includes a primary cache characterized by a virtual index and physical tags, and a secondary cache characterized by a physical index and physical tag. Thus, the cache system forms a hybrid of physical-cache and virtual-cache characteristics. Further, the secondary cache includes a primary index segment for each line of secondary cache. The primary index segment corresponds to a portion of the virtual address for the contents stored at the respective secondary-cache line. Further, primary cache is maintained as a subset of secondary cache. To maintain the primary cache in such a way, the primary index segment is used to generate an index into primary cache to identify each potential primary-cache block which may be a subset of a secondary-cache block to be changed. When a secondary-cache block is to be invalidated, flushed or overwritten, the corresponding primary-cache blocks are identified and invalidated.

Abstract: An apparatus and method for interactively magnifying a base texture to generate a generally unblurred magnified image of the base texture is disclosed. The present invention includes a base texture generator for filtering a high resolution source image to generate a base texture. A detail texture generator extracts a representative portion of high frequency information from the source image to generate a detail texture, wherein the detail texture comprises the extracted representative portion of high frequency information. An image magnifier, which is coupled to the base texture generator and the detail texture generator, augments the generated base texture with high frequency information from the detail texture to thereby generate a magnified image of the generated base texture at a particular level of detail.

Abstract: A bracket for securing a daughter card within a computer housing. The computer housing having a housing base. The bracket having a bracket base. The bracket base having a base tab for slidably securing the bracket to the housing base. The bracket also has a securing means for engaging the daughter card and for securing the daughter card. The securing means has a first slot for accepting the daughter card and a second slot, perpendicularly aligned at a first end of the first slot, for accepting the daughter card and for directing the daughter card into the first slot.

Abstract: An electronic logic and computer implemented apparatus and method for accessing graphic geometric data within a computer display system utilizing an SIMD environment. The present invention spreads the vertex data structure of geometric primitives across multiple memories allowing much higher bandwidth access into the data structure for greater performance. The present invention eliminates branches from the processing of triangle and quadrilateral primitives allowing full utilization of SIMD processors. The present invention utilizes an indirection circuit and software to control the order of coupling of these memory units to the inputs of specialized graphic processors. Therefore, the indirection mechanism allows a geometric data structure to be spread across multiple memories in a multi-memory/multi-bus environment with indirection across these multiple busses and memories.

Abstract: A programmable video output format (VOF) generator that enables a processing system to drive different video display devices with varying video format requirements. The programmable VOF generator includes a compiler that generates video formats based on user input, and a state machine that generates all video signals with requisite output format. The compiler allows the user to provide minimal information on general display parameters using a high-level language. Therefore, no specialized knowledge of the video display hardware requirements is required from the user.

Abstract: A system and method of interactively magnifying a first texture to generate a generally unblurred high resolution display image at a particular level of detail are disclosed. The method of the present invention includes the step of extrapolating from the first texture and a second texture to generate an extrapolated frequency band. The extrapolated frequency band approximates high frequency image information contained in a texture of higher resolution than the first texture. The method also includes scaling the extrapolated frequency band as a function of the particular level of detail to generate a scaled extrapolated frequency band, wherein the scaled extrapolated frequency band approximates high frequency image information contained in a magnified image of the first texture at the particular level of detail.

Abstract: A method is provided which sharpens three-dimensional images by using an unsharp masking technique subsequent to interleaving and before printing.

Abstract: A high performance shared-bus signal detection mechanism comprises a plurality of access event registers, an address comparator, an event masking component, and a local processor access detector. The comparator component couples to a bus providing access to a shared memory address space. The bus can be used by a single processor or shared by a plurality of processors. A processor loads the address event registers with address base and extent values and type of access notification desired. As addresses and access-type signals appear on the bus, the comparator simultaneously compares the bus information to access event register information to determine if the bus access meets access event register criteria. When matches occur, the comparator emits an appropriate signal to an event masking component. The local processor also loads the event masking component to selectively mask off unwanted event notifications as well as those performed by itself.

Abstract: A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended versions of m-bit entities, produce an N-bit result that may not correspond to the correct m-bit result, sign-extended to N bits. For these instructions compatibility requires that the instructions be further defined to guarantee a sign-extended result. This means that separate N-bit instructions corresponding to these m-bit instructions are needed. The support for up to an N-bit virtual address space is provided in part by widening the virtual address data paths.

Abstract: A system for abstracting the byte ordering of a computer firmware from the operating system by allowing a computer to automatically change endianness under full software control. The byte ordering can be switched completely transparent to the end user during system boot. The system is comprised of hardware and software to run either byte order stand alone software or operating systems on demand.

Abstract: A method and apparatus for enabling a computer to run using either a Big Endian or Little Endian architecture is provided. The method and apparatus use the fact that XORing the lower two bits of a byte address in one architecture with a binary 3 converts that byte address to the equivalent byte address in the other architecture. The conversion method and apparatus is implemented in hardware by setting a bit in a status register indicating a Big Endian or Little Endian architecture in conjunction with an XOR gate which couples the byte address to binary 3. The conversion method and apparatus is implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and XORing the two least significant bits of the byte address with a binary 3.

Abstract: A method and apparatus for controlling the storage of display information into a frame buffer is disclosed. A memory means is provided for storing information for controlling the storage of display information into the frame buffer where the memory means contains a plurality of locations each of which corresponds to and controls the storing of display information in one location of the frame buffer. A pass/fail ALU is coupled to the memory means to obtain a value for a particular pixel; this ALU provides a signal indicative of one of a first or second state which state indicates whether storage of display information to the frame buffer will occur. A first function is stored in a register, which function specifies the first signal. A first storage register and a second storage register store a second function and a third function respectively and provide a second value and a third respectively.

Abstract: An apparatus and a method of generating video timing information and display ID information wherein the video timing generator includes a memory, typically a random access memory, which stores video timing information. A control logic device couples the information from memory to a FIFO. The control device further couples the initial information from the FIFO to a second memory, typically a register, and a sequential counter. After initial loading of information in the second memory and sequential counter, the sequential counter determines when the second memory and itself will be loaded with the next set of information. Once the sequential counter reaches zero, it generates a signal enabling itself and the second memory to load the next set of information. The display ID generator includes a memory which stores display ID information. A control logic device couples the information from the memory to a first FIFO.

Abstract: In a computer graphics system, a method of generating a geometrically valid point sample mask corresponding to a pixel. A separate mask is generated for each edge of a polygon. These masks specify whether particular subsample points are within a half-plane defined by an edge of the polygon. This information is determined by examining the sign of vertical or horizontal distance metrics corresponding to those sample points. These separate masks are merged to form the final point sample mask. Thereby, the final point sample mask contains information specifying whether particular sample points reside within the polygon. This information is used in rendering the pixel for display by the computer graphics system.

Abstract: A method for determining the coverage of a pixel, which includes determining a function of the distance from the currently sampled point to each edge of a polygon and then adding a predetermined value to the value of the function. This value is then clamped according to a function which provides an output of a predetermined value if the input to the function is not within a predetermined range and otherwise provides the value of the input if the input is within the predetermined range. The coverage of the pixel by the polygon is computed by multiplying the clamped functions. Blending the parameter values is performed if the value of the coverage falls within a predetermined range; otherwise, no blending occurs.

Abstract: A cursor generator for use in a computer system having a high pixel clock rate. The cursor generator includes a first memory which stores a line of the cursor for display on the display device and a second memory which stores the entire cursor. The data for the line of the cursor can be more quickly retrieved from the first memory than from the second memory, and the first memory is clocked under the control of the high pixel clock rate while the second memory is clocked at a slower clock rate. A controller couples data for the one line of the cursor from the second memory, which is typically dynamic random access memory to the first memory which is typically a high speed register or a combination of registers and multiplexors. The controller couples the data for one line at a time of the cursor to the display device in order to display the cursor in conjunction with the rest of time image displayed on the display device.