Abstract: A computer based system and method for implementing a read-modify-write operation in a computer based system comprising a first bus and a second bus, wherein the second bus is not transaction based. The method includes the steps of determining whether a first device connected to the first bus has issued on the first bus a read transaction comprising a predetermined trigger address, acquiring the second bus in accordance with the determination, reading data via the second bus from a second device connected to the second bus after the second bus has been acquired, modifying in a predetermined manner the data read from the second device, writing the modified data to the second device via the second bus, and releasing the second bus after the modified data has been written to the second device via the second bus.

Abstract: A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instruction and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.

Abstract: A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.

Abstract: A method and apparatus for drawing at least a one pixel wide antialiased line on an edge of a filled polygon. The apparatus comprises an interpolator, having a set up unit and an iterator unit, and a blender. The set up unit determines various parameters of the line to be drawn and selects a pair of pixels adjacent to and straddling an idealized line representing the line to be drawn, where the first pixel is claimed by the edge of the polygon as a filled pixel. The iterator unit determines the coverages of the second pixel based on the parameters output by the set up unit. The blender determines the color intensity value of the second pixel as a function of its coverage and writes the color value into a memory. The apparatus also incorporates methods for antialiasing polygon meshes and resolving accumulation error in the derivation of each pixel's position.

Abstract: A method and apparatus are presented for displaying three-dimensional navigable display space containing an aggregation of graphical objects and an overview of the aggregation of display objects. An altered perspective is provided by compressing the horizontal dimension of the displayed objects so that a user can see a representative overview of the entire aggregation of display objects that have been selected for display together on a display screen. The compressed component is expanded so that the objects appear wider as a navigator approaches the displayed objects. A spotlight shines down on objects responsive to a data query. The spotlight serves as a navigation aid to the navigator so that highlighted items are visible from a distance and can be easily located.

Abstract: An image processor is provided which rasterizes polygons with a minimum of computation. Pixels are tested for being inside a triangle by sorting the vertices by their values in one coordinate, rounding the vertices to the nearest pixels, and calculating two characteristic functions for pixels one scan line at a time, thereby identifying two end pixels for the scan line, where the particular functions used are edge characteristic functions for the two edges which bound pixels in the scan line within the triangle defined by the rounded vertices. To avoid ambiguity, pixels on one end of a scan line are deemed outside the triangle if they are exactly on the edge. Alternatively, only one function per pixel is used, the edge function for the nearest edge. The rasterization process is extensible to polygons of more than three sides, by taking into account that only two sides of the polygon need to be considered for a given scan line, and thus only two characteristic functions are needed at any one time.

Abstract: A computer implemented method of annotating a geometric figure displayed and manipulable in three-dimensional representation on a display of a computer system with a pointer is described. The pointer is also displayed and manipulable in three-dimensional representation on the display. The method associates multimedia functions with the geometric figure. The pointer is positioned to point at an area of the geometric figure using a control device. The geometric figure is displayed in a particular view orientation when the pointer points at the area of the geometric figure. The pointer is then oriented three-dimensionally such that the pointer can point at the area of the geometric figure at a desired angle. The particular view orientation of the geometric figure with the pointer can be preserved such that the particular view orientation of the geometric figure with the pointer can later be retrieved. The pointer can be activated by attaching a marker to the pointer using the control device.

Abstract: A set associative translation lookaside buffer (TLB) that supports variable sized pages without requiring the use of a separate block TLB. The TLB includes a hashing circuit that creates an index into the TLB for a virtual address using different bits from the virtual address depending on the page size of the address, and a comparator that compares virtual address identifiers or portions of virtual address identifiers stored in the TLB to the current virtual address to determine if a translation to the current virtual address is stored in the TLB.

Abstract: A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.

Abstract: A system for abstracting the byte ordering of a computer firmware from the operating system by allowing a computer to automatically change endianness under full software control. The byte ordering can be switched completely transparent to the end user during system boot. The system is comprised of hardware and software to run either byte order stand alone software or operating systems on demand.

Abstract: A method for rendering a three dimensional graphic object in a two dimensional display space by segmenting the object into parallelepipeds and decomposing the parallelepipeds into rods of voxels that are parallel to the depth axis (Z) of the display and by projecting the rods of voxels onto the X-Y plane of the display as lines of pixels and a method for drawing antialiased volumetric images. An apparatus for implementing both methods includes an interpolator, having a set-up unit and an iterator unit, and a blender. The set-up unit determines various parameters of the image to be drawn, including the total number of voxels to be blended together into each pixel to be drawn, and selects a pixel pair adjacent to and straddling an idealized line representing a line to be drawn. The iterator unit determines the coverages of the pixel pair based on parameters output by the set-up unit.

Abstract: A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.

Abstract: A multi-domain, distributed arbitration system, and a method performed by a plurality of arbiters to control arbitration of requests for a multiprocessor system bus. The requests are generated by a plurality of nodes coupled to the multiprocessor system bus. The requests are presented on a plurality of arbitration request lines. Each node comprises one of the arbiters such that each arbiter is associated with a corresponding node. A plurality of domains are created by the arbiters based on a bit-wise combination of the requests on the arbitration lines. A priority is assigned to each domain relative to the other domains. Each arbiter monitors the requests on the arbitration request lines and generates an i.sub.-- win result that indicates whether or not the associated node is an overall arbitration winner if a request from that node is pending. In addition, the arbiters generate a who.sub.-- won result that indicates which node was the overall arbitration winner according to the assigned priorities.

Abstract: A computer-implemented method of transmitting images from a transmitter to a receiver (e.g. in a teleconferencing application). A receiver maintains an image in a local storage (e.g. that from a previous frame in a sequence of frames) and the transmitter receives an updated image for a next temporal period (e.g. the next frame). The transmitter divides the updated image into blocks and comparing a rotating pixel sample(s) of each of the blocks from the updated image with a sampled pixel from a local copy of a receiver's image at a same spatial position of the pixel sample(s). The transmitter determines a difference between the rotating sampled pixel of each of the blocks from the updated image and the local copy of the receiver's image. It stores a reference to the block and associates the difference with the reference. The difference is an average absolute difference in luminance between the two blocks.

Abstract: A compact dual function adder circuit for providing both an addition operation for adding an input m-bit word to an input n-bit word, wherein m<n, and an increment operation for incrementing the input n-bit word, the dual function adder comprising a n-bit incrementer circuit, wherein the n-bit incrementer includes a first m-bit incrementer and a second n-m)-bit incrementer to provide a n-bit incrementer output sum. The n-bit incrementer output sum comprises an m-bit incrementer output sum from the m-bit incrementer and a n-m)-bit incrementer output sum from the n-m)-bit incrementer.

Abstract: A multiprocessing system that uses read resources to track cache coherent split transactions on its main system bus. Pending reads are tracked by being associated with read resources. When a read request is issued, it occupies the first available read resource. A pending read request will occupy a read resource until a corresponding read response appears on the bus. If all read resources are filled, future read requestors must wail until a read resource becomes available.

Abstract: A method and circuit providing for an accurate sampling of data on a high speed bus in a computer system. Utilizing a single clock source, functional units that are capable of supporting two clock input sources, and a routing technique that provides for a receiving unit to be clocked prior to a transmitting unit, data transfer can occur reliably and economically on a high speed bus. Synchronization within a particular unit is accomplished by providing serial edge-triggered registers that are triggered by the respective clock inputs.

Abstract: A mechanism for dividing an integer dividend by an integer divisor to generate an integer quotient operates by aligning the divisor relative to the dividend such that a right-most bit of the divisor is aligned with a bit M of the dividend. The divisor is compared to an integer value whose right-most bits are equal to bits of the dividend which are aligned with bits of the divisor. As a result of this comparison, quotient bits which positionally correspond to the dividend bit M and to bits of the dividend which are located to the left of the dividend bit M are cleared to zero. Also as a result of the comparison, the dividend is divided by the divisor as aligned relative to the dividend to thereby generate values for any uncleared quotient bits.

Abstract: An error detection system wherein 64 bits of data word are protected by 8 check bits which yield 8-bit syndromes. Single-bit errors are indicated by syndromes that contain exactly three "1"s or by syndromes that contain exactly five "1"s in which bits 0-3 or 4-7 of the syndrome are all "1." Single-bit errors that occur from faulty check bits are indicated by syndromes that contain exactly one "1." All two-bit errors, and four-bit errors within a nibble, are indicated by syndromes that contain an even number of "1"s (i.e., an even number of "1"s). Three-bit errors within a nibble are indicated by syndromes that contain five "1"s in which bits 0-3 of the syndrome and bits 4-7 of the syndrome are not all "1." Four-bit errors within a nibble are indicated by syndromes that contain four "1"s. In another embodiment of the invention, 25 bits of data word are protected by 7 check bits yielding 7-bit syndromes.