Abstract: A method for scan converting a triangular polygon where information representative of parameter values at each vertex is provided. The method includes the step of selecting an edge of the triangular polygon which is designated as a major edge and calculating parameter values for a first pixel center adjacent to the major edge, and then moving to a next pixel center adjacent to the major edge and calculating parameter values for that next pixel center adjacent to the major edge. The method continues to find pixel centers adjacent to the major edge until all parameter values for pixel centers adjacent to the major edge have been calculated. Then, for each line parallel to an orthogonal axis of the display device which is intersected by the triangular polygon, the method interpolates parameter values for pixel centers within the triangle which have not been calculated by interpolating from the calculated parameter values for one pixel center for each line. Typically, a line is column or a scan line.

Abstract: An apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of memory. An example of the second type is the processing of a non-memory-access instruction. The apparatus may further include failsafe circuitry to shut down the TLB if at least a given number of matches occur at any time and for any reason, the given number being greater than 1. The apparatus prevents loss of data or damage to the chip where match comparisons are performed in parallel.

Abstract: A device for installing and removing a removable computer component, such as a data storage drive or computer card, into or out of a computer housing. The device features a drive sled to which the data storage drive is mounted. A stationary carrier tray is secured to the computer housing. Interlocking angled tracks on the drive sled and the carrier tray secure the two structures together. To promote easy coupling of the drive's electrical interface connectors, the front end of the drive sled has a floating guide plate with forward-projecting locating pins, which pins are used to align the electrical connectors held by the floating guide plate. A rack and pinion mechanism is provided. The rack is disposed on the top of the carrier tray while the pinion is located on the underside of the drive sled. As the drive sled slides onto the carrier tray, the lever-actuated pinion gear engages the rack and consequently displaces the drive sled relative to the stationary carrier tray.

Abstract: Techniques for providing a number of precisely synchronized clock signals at a number of different frequencies at each of a plurality of locations on a chip. A number of synchronized clock signals are generated at an initial location on the chip, and distributed to the various locations with relative delay times that are equal to within a precision, which may be less than the ultimate precision required. A single synchronization signal is also generated at the initial location, and is distributed to the remote locations with delay times that are equal to each other to a precision that corresponds to the precision required of all the clock signals. Separate synchronization circuitry at each remote location receives the clock signals and the synchronization signal, and resynchronizes the clock signals to the precision with which the synchronization signal was distributed. The set of lines is configured as a tree structure.

Abstract: A method is provided which sharpens three-dimensional images by using an unsharp masking technique subsequent to interleaving and before printing.

Abstract: A binary shifter which utilizes shifter control logic to shift a 64-bit binary word by shift amounts up to 63 bit positions using a pre-multiplexer and shifter array configuration capable of shifting up to 32 bit positions. The shifter control logic executes two cycles of shifting operations to achieve shift amounts greater than 32 bits. An improved shifter pre-multiplexer and array for shifting 64-bit binary words by up to 32 bit positions in one cycle is disclosed. The improved shifter pre-multiplexer and array uses 9:1 pre-multiplexer cells with tristate outputs to place input data on selected discrete sections of horizontal data lines allowing for a reduced number of cells and control lines.

Abstract: A graphical display system and a method for Z-subdivision of polygons into quadrilaterals and triangles whose vertices are arranged between two adjacent Z planes. This slicing allows both atmospheric and texture parameters to be interpolated linearly with minimal error within each quadrilateral or triangle slice. Object data from a host computer is processed by four pipelined graphics subsystems before being displayed on a display screen. Each object is decomposed into a set of primitives. Each primitive may intersect one or more Z planes thereby producing a set of component portions of the primitive. Once a primitive is sliced into component portions, a texture is mapped onto each component portion by interpolating texture parameters to points on or within the component portion. Finally, the textured component portions are rendered on a display device thereby creating a seamless complete object.

Abstract: A server to which clients subscribe for on-the fly notice of alterations to files and directories in a computer having an operating and file management system. The server also provides status of the execution state of executable code, alteration detection for multiple requests from multiple clients, and tracks files and directories on a user's local station. In addition, the server monitors network-mounted files on remote computers even though events are only generated for local activity on network files.

Abstract: A dynamic random access memory (DRAM) single in-line memory module (SIMM) having optimized physical dimensions achieves high speed and high storage capacity. The DRAM SIMM has a printed circuit board with a multi-contact connector, a plurality of DRAM sets, each set having a plurality of DRAM chips mounted on the printed circuit board, and a plurality of buffers which are also mounted on the printed circuit board. The number of buffers is equal to the number of DRAM sets. Various standard DRAM chips can be used on the SIMM to achieve different performance and storage capacity, while maintaining plug compatibility of the multi-contact connector with a memory board. The buffers buffer the control and address signals for the DRAM chips, which is necessary to keep control and address signal integrity due to the number of DRAMS. The buffers permit each DRAM to receive the necessary control and address signals in a more synchronized fashion, so that relative delays are well controlled.

Abstract: An assembly that couples a removable computer component to a computer is disclosed. The assembly has a disk drive or other similar device that is mounted onto a frame and is insertable into the opening of a computer housing. At one end of the opening is a first electrical connector mounted onto a rear wall of the housing. The disk drive is coupled to a second connector mounted onto the front end of the frame. The frame is inserted into the opening until the second connector mates with the first connector, thereby electrically coupling the disk drive to the computer.The housing includes a bearing extending from a support plate that structurally supports the frame and disk drive. The bearing is adapted to be engaged by a lever that is pivotally connected to the frame. The disk drive is secured to the housing by rotating the lever from a first position to a second position, such that the lever latches onto the bearing.

Abstract: A method and apparatus for controlling the storage of display information into a frame buffer is disclosed. A memory means is provided for storing information for controlling the storage of display information into the frame buffer where the memory means contains a plurality of locations each of which corresponds to and controls the storing of display information in one location of the frame buffer. A pass/fail ALU is coupled to the memory means to obtain a value for a particular pixel; this ALU provides a signal indicative of one of a first or second state which state indicates whether storage of display information to the frame buffer will occur. A first function is stored in a register, which function specifies the first signal. A first storage register and a second storage register store a second function and a third function respectively and provide a second value and a third respectively.

Abstract: A method for accelerating the writing of data to a Z buffer including the steps of reading the Z value presently stored at a position in the Z buffer; writing a new Z value to the position in the Z buffer if the result of a last available comparison in a sequence of comparisons wrote a new Z value to a position in the Z buffer, writing the Z value read back to the position in the Z buffer if the result of a last available comparison in a sequence of comparisons wrote the Z value read back to a position in the Z buffer, and comparing the Z value read from the position of the Z buffer with the new Z value; and rewriting the correct value to the Z buffer if the comparison of the Z value read from the position of the Z buffer with the new Z value demonstrates that the value written was incorrect.

Abstract: A translation look-aside buffer with a variable page size per entry is disclosed. Each entry can have a different number of bits translated from a virtual address to a physical address. Each entry in the TLB contains an indication of the page size for that entry. When the translation is done, the indication of page size determines how many bits are translated.

Abstract: A method for performing a transfer of digital information. A starting address is sent from a central processing unit of a digital computer to a bus, to a memory, and to a subsystem. A word count is sent from the central processing unit to a bus and to a subsystem. A block of data having a starting address that is the address of a first word in the block of data and having a word count that represents the number of words in the block of data is sent directly from the memory to the subsystem via the bus.

Abstract: Apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of memory. An example of the second type is the processing of a non-memory-access instruction. The apparatus may further include failsafe circuitry to shut down the TLB if at least a given number of matches occur at any time and for any reason, the given number being greater than 1. The apparatus prevents loss of data or damage to the chip where match comparisons are performed in parallel.

Abstract: A graphical display system and process for specifying and controlling a display range in which a specified form of texture mapping is applied or suppressed. Object data from a host computer is processed by four pipelined graphics subsystems before being displayed on a display screen. These graphics subsystems include: 1) a Geometry Subsystem, 2) a Scan Conversion Subsystem, 3) a Raster Subsystem, and 4) a Display Subsystem. Span Processors within the Scan Conversion Subsystem manipulate pixel coordinates in order to handle sitations when coordinates are located out of range of a texture map. Processing logic and hardware registers located within each Span Processor implement two texture modes for handling out-of-range coordinates. First, a mask and comparison register is provided to hold a value specifying a selected range in which texture is applied to a pixel. If a pixel is outside the specified range, texture application is suppressed.

Abstract: A tool for characterization of files in a computer having an operating and file management system is described. The tool provides consistent definition and design of the functionality and appearance of icons and symbols used with operating environment programs.

Abstract: A translation of a portion of a virtual page number to a portion of a physical page number in a "TLB slice." The slice translation is used to index into a physical cache memory which has virtual tags in addition to physical tags and whose addresses are physical. By comparing the virtual tag to the input virtual address page number, it can be determined whether there was a hit or a miss in the combination of the TLB slice and the cache memory. By translating only a few bits of the virtual address to a few bits of a physical address, the speed of the device is greatly enhanced. This increased speed is achieved by making the TLB slice direct-mapped and by taking advantage of its small size to build it with special hardware (either high-speed RAM (random access memory) or with latches and multiplexers). There is no separate comparison at the TLB slice output for determining a TLB slice hit.