Abstract: A computer-implemented method of transmitting images from a transmitter to a receiver (e.g. in a teleconferencing application). A receiver maintains an image in a local storage (e.g. that from a previous frame in a sequence of frames) and the transmitter receives an updated image for a next temporal period (e.g. the next frame). The transmitter divides the updated image into blocks and comparing a rotating pixel sample(s) of each of the blocks from the updated image with a sampled pixel from a local copy of a receiver's image at a same spatial position of the pixel sample(s). The transmitter determines a difference between the rotating sampled pixel of each of the blocks from the updated image and the local copy of the receiver's image. It stores a reference to the block and associates the difference with the reference.

Abstract: A system and method for compiling and linking a source file is described. A compiler generates class information pertaining to object-oriented classes referenced in the source file. The class information is sufficient to enable a linker to resolve class definitions and to perform class relocation operations. The compiler also generates an object file from the source file. The object file includes the class information. The compiler generates the object file such that resolution of class definitions and performance of class relocation operations are delayed until operation of the linker. A linker links the object file potentially with at least one other object file or shared library to thereby generate an executable file or shared library. The linker uses the class information contained in the object file to resolve class definitions and to perform class relocation operations.

Abstract: A synchronizing device is described. The synchronizing device detects a video frame. The synchronizing device determines a duration of a first signal state of a video signal, determines a duration of a second signal state of the video signal and compares the duration of a first signal state with the duration of a second signal state.

Abstract: A system and method for controlling the flow of messages transferred between modules of a computer system is disclosed. The system includes a receiver module comprising a buffer having a capacity to store a predetermined number of messages, and a transmitter module coupled to the receiver module. The transmitter module includes a counter for maintaining a count value representative of free space in the buffer. The transmitter module transmits a message to the buffer when the count value is greater than zero. Then, the transmitter module decrements the count value by a value characteristic of the transmitted message, such that the count value is updated to be representative of free space in the buffer after transmission of the message to the buffer.

Abstract: A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. A bypass circuit for bypassing the second instruction storing circuit is also provided.

Abstract: An overhead projector for use with a flat panel display assembly. The specialized overhead projector provides cooling for the LCD flat panel when used in an overhead projection configuration. The projector contains a rail on which the flat panel display is positioned for alignment and to provide air passage there through for cooling. A clamping mechanism is also described for securing the flat panel display to the projector. The flat panel display is a back-lit flat panel display subsystem for direct viewing as a monitor and also has overhead projection capability. The display subsystem contains a removable door assembly which provides for back-lighting for direct viewing. When the door assembly is removed, the active matrix LCD is semi-transparent and can be placed over the imaging screen of the overhead projector such that the LCD color image can be thus projected.

Abstract: A method and apparatus for restarting an instruction processing pipeline after servicing one or more interlock processing faults. A pipeline architecture is defined in which processing interdependencies (such as instruction latencies, resource conflicts, cache accesses, virtual address translations and sign extend operations) are presumed not to be present so as to increase pipeline throughput. Interdependencies which actually occur appear as processing faults which then are serviced. At the completion of the servicing, pipeline restarting operations occur, during which the portions of the pipeline which are invalidated are preloaded. Preloading includes backing-up the invalidated stages and re-executing such stages with corrected information so as to fill the pipeline. The pipeline portions (e.g., stages) which are invalidated are determined by the type of processing fault which occurs. Upon completion of preloading, normal instruction pipeline processing resumes.

Abstract: A graphics memory apparatus and methods for the organization, storage and playback of graphics data for display purposes. The image data and overlay data (and/or other graphics data) are organized and stored in the graphics memory in an interleaved fashion so that only one type of graphics data is stored at any one memory address (pixel data or overlay data or other graphics data) and so that preferably full memory capacity is utilized for the area of graphics memory employed. As an example, in a system for displaying eight bits of color image data and two bits of overlay, the overlay data is interleaved with the image data so that four consecutive address locations will contain image data, with preceding or following address location containing the associated overlay data. Therefore, such organization can result in graphics memory efficiency, reduced bandwidth requirements therefor and increased speed with which the contents or portions thereof may be loaded, altered, etc.

Abstract: A method and apparatus for drawing at least a two pixel wide antialiased line is described in which the apparatus utilizes an interpolator, having a set up unit and an iterator unit, and a blender. The set up unit determines various parameters of the line to be drawn and selects a pair of pixels adjacent to and straddling an idealized line representing the line to be drawn. The iterator unit determines the coverages of the pair of pixels based on the parameters output by the set up unit. The blender determines the color intensity values of the pair of pixels as a function of the coverages and writes the color values into a memory. The memory is a frame buffer type memory utilized to drive a display and is split into at least four banks so that the color values of the pair of pixels can be simultaneously stored in different memory banks.

Abstract: A TLB which has at least two page frame numbers (PFN) associated with each tag (Virtual Page Number) is provided. Thus, a match will produce two possible physical page frame numbers. The selection between these two is controlled by a bit provided directly from the virtual address, without translation. This bit is preferably the least significant bit of the virtual page number, or the first bit after the physical offset. This structure effectively doubles the capacity of the TLB without doubling the number of tags. Although the virtual space covered by each tag or VPN is necessarily restricted to two contiguous areas, the invention allows these two contiguous areas to be mapped to completely different regions of the physical address space. In addition to limiting the number of tags required, the number of comparators required is also similarly limited, with only the number of physical page frame numbers stored being required to double.

Abstract: A method and computer program-product for converting a program designed to be executed on a computer system employing a first predefined memory order, such as the Big Endian architecture, to a program which is executable on a computer system employing a second predefined memory order, such as the Little Endian architecture. The method and computer program-product uses the fact that performing a logical operation on the lower two bits of a byte address in one architecture converts that byte address to the equivalent byte address in the other architecture. The method and computer program-product are implemented in software by scanning the instructions of the input for load and store instructions.

Abstract: A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache to determine if a forced atomic (FA) instruction is in a second level cache pipeline. If an FA instruction is determined to be in the second level cache pipeline, then interventions to the second level cache are delayed until the FA instruction exits the second level cache pipeline. In this manner data written by operation of cache memory access instruction that cause the interventions is not destroyed by the execution of the FA instruction, thereby preventing data loss. The method also monitors the second level cache pipeline to determine if a possible miss (PM) instruction is in the second level cache pipeline.

Abstract: A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended versions of m-bit entities, produce an N-bit result that may not correspond to the correct m-bit result, sign-extended to N bits. For these instructions compatibility requires that the instructions be further defined to guarantee a sign-extended result. This means that separate N-bit instructions corresponding to these m-bit instructions are needed. The support for up to an N-bit virtual address space is provided in part by widening the virtual address data paths.

Abstract: A RISC processor utilizes a segmented cache to reduce word line loading to reduce power consumption and increase speed. Address bit are predecoded to activate a selected segment. Groups of instructions are accessed from the cache in parallel and stored in register. The stored instructions are fetched from the register during sequential instruction execution to reduce the number of cache accesses.

Abstract: A bracket for securing a computer drive within a housing. The housing has a housing base, and two housing walls each disposed perpendicularly to the housing base and to each other. The bracket comprises a base for supporting the computer drive. The base has a first base aperture for slidably securing the bracket within the housing and for preventing movement of the bracket in a first degree of freedom. The bracket also comprises a first support means, which is perpendicularly coupled to the base, for engaging the first housing wall and for preventing movement of the bracket in a second degree of freedom. Perpendicularly coupled to the base is a first means for engaging the second housing wall and for preventing movement of the bracket in a third degree of freedom. The bracket further comprises a second support means which is perpendicularly coupled to said base. The second support means has an interior surface facing an interior surface of the first support means.

Abstract: A system and method of generating object code from an intermediate representation of source code is described. The intermediate representation includes a plurality of basic blocks each being represented by a plurality dam dependency graphs, wherein each data dependency graph comprises a plurality of nodes each corresponding to an instruction from the target computer instruction set. The present invention operates by selecting a source basic block (that is one of the basic blocks of the intermediate representation) and a target basic block (that is another of the basic blocks of the intermediate representation), and by identifying a maximal set of instructions contained in the source basic block that are movable from the source basic block to the target basic block without violating any data dependency relationships of the data dependency graphs. An overall cost model of aggregately moving instructions of the maximal set from the source basic block to the target basic block is generated.

Abstract: Methods and apparatus for optimizing the operation of an instruction pipeline in a computer are disclosed. The methods and apparatus function at both the effective beginning and end of the pipeline. At the pipeline's beginning, a Pipeline Controller monitors the availability of data for various floating point operations. Data is read at either a fast or slow rate, depending on its availability, and instructions are allowed to proceed through the pipeline based on this data availability. At the effective end of the pipeline, the Controller monitors all instructions in the pipeline, notes all potential resource conflicts, and resolves these potential conflicts by either the insertion of an appropriate number of HOLD states or the conclusion that no actual resource competition exists.

Abstract: A method and apparatus for navigating within a three dimensional graphic display space and manipulating information and data represented by objects in display space. The method and apparatus presents users with a vastly expanded view of their data, displayed with a richer dimensionality. Data objects represented by graphic objects are arranged into a navigable landscape representing the containership and contextual relations of the underlying data. The graphic objects are columns, pedestals and disks, which represent data blocks, cells, and comparative values respectively. The columns rest on the pedestals. The disks are located with respect to the top of the column to signify a comparative attribute. The pedestal rest upon a ground plane. The ground plane represents a threshold value. Data attributes may be represented by visual, textual, executable, or audible characteristics of the display.

Abstract: In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.