Abstract: The image data are coded with field DCT or frame DCT depending on the characteristics of the image data. However different coding types will result in different boundary marks of boundaries between adjacent blocks or adjacent macro blocks. Therefore the de-blocking of a boundary between two adjacent blocks or adjacent macro blocks should be performed according to the format of image data and the coding type of the adjacent blocks or adjacent macro blocks.

Abstract: A diversity receiver includes N number of Fourier transform circuits, N number of channel estimators, N number of match filters, N number of soft demappers, a combination/selection unit, and a channel decoder. The diversity receiver merges the square of the absolute value of estimate channel frequency response and transmission data into a demodulation signal and then outputs the demodulation signal by means of the match filter.

Abstract: A decision feedback equalizer having a adjusting device and method thereof are described. The decision feedback equalizer having an adjusting device includes a feed-forward filter, a decision device, a feedback filter, the adjusting device, and a summation device. The feed-forward filter generates a forwarding signal (Sff) based on an input signal (Si). The decision device generates a first decision (Sd1) signal and a second decision signal (Sd2) which are associated with the summation signal (Ssu). The feedback filter receives the second decision signal (Sd2) for generating a feedback signal (Sfb). The adjusting device adjusts the first decision signal (Sd1) according to a first weighting value (V1) for generating a first adjusted signal (Sa1) and transmitting the first adjusted signal (Sa1) to the feed-forward filter. The adjusting device further adjusts the feedback signal (Sfb) according to a second weighting value (V2) for generating a second adjusted signal (Sa2).

Abstract: The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine intervals to cover a range which is larger than the length of one coarse interval. Each coarse interval comprises some extra fine intervals which are exceeded the boundary of the coarse intervals in one side. The heavy switching will be postponed until the extra fine intervals are used up. In the meantime, the fine calibration unit records the number of extra fine interval which be used. An extra-boundary value will be recorded in the fine calibration unit for determining an initial fine interval in another coarse interval if the heavy switching occurs. It should be noted that the extra-boundary value could be a positive or minus value corresponding to which a forward coarse interval or a backward coarse interval the reference signal drifts into.

Abstract: An image compression device includes a floating-point texture-loading unit, a shader, a RGB to YCrCb compressor, and a parameter adjusting unit. The floating-point texture-loading unit receives raw image data that includes N number of RGB pixels. The shader receives the raw image data and shades the N number of RGB pixels. The RGB to YCrCb compressor receives the shaded image data and calculates the brightness/chroma value of each of the RGB pixels, wherein the chroma value of the RGB pixel having the smallest brightness value among all the RGB pixels is selected as a common chroma value for all the RGB pixels. The parameter adjusting unit receives and adjusts N number of brightness values of the RGB pixels and the common chroma value and stores them in a form of compressed image data into a memory.

Abstract: A pixel processing system includes a register-collecting mechanism and a pixel shader. The register-collecting mechanism corrects a first program to a second program. The first program requires a number of first registers. The second program requires a portion of the first registers of the first program. The pixel shader executes the second program. A method for register-collecting mechanism comprises the steps of: scanning the first instructions of the first program; decoding the first instructions to obtaining a plurality of first register numbers of busy register group of the first program; correcting the first program to a second program which only occupies the busy register group. As a result, the idle register group of the first program is available to be reallocated to the additional piled in pixels. Thus the pixel processing system can process more pixels in a batch using a given number of registers, and longer texture load latency can be hidden.

Abstract: The present invention discloses re-configurable data transmission ports with data-integrity transaction controlling unit in a computerized computer and the method for performing the same. The controlling unit further includes a port-configuration detecting mechanism and a buffer-configuration subunit. The port-configuration detecting mechanism can inspect configuration status of all of the first ports on variance of data transmission bandwidths, e.g. “merge” or “spilt” status. The buffer-configuration subunit upon different configuration status of each first port configures each retry buffer. When a specific first port is configured on “merge” status, the buffer-configuration subunit can follows up to configure the retry buffer owned by the specific first port and the retry buffers owned but disused by the other first ports to constitute a buffer group with merging of storing spaces of said configured retry buffers.

Abstract: An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel processing system comprises an instruction folding mechanism and a pixel shader. The instruction folding mechanism folds a plurality of first instructions in a first program to generate a second program having at least one second instruction which is a combination of the first instructions. The pixel shader connected to the instruction folding mechanism fetches the second program to decode at least the second instruction having the combination of the first instructions to execute the second program. The instruction folding mechanism comprises an instruction scheduler, a folding rule checker, and an instruction combiner. The instruction scheduler connected to the folding rule checker is used to scan the first instructions according to static positions in order to schedule the first instructions in the first program.

Abstract: A method of balancing the path delay of a clock tree for minimizing clock skew of the clock tree in the IC layouts is described.

Abstract: A method and apparatus for detecting the transmitted mode and guard interval length. The mode detection is adopted by the DVB-T system to increase system flexibility and combat multi-path interference in the transmission environment, of the received OFDM signals by applying the concepts of down-sampling and correlation. The unique combination of down-sampling and correlation method requires far less memory than the traditional correlation methods. By comparing the indicators resulting from output of each correlation module, the transmitted mode and guard interval length are detected with much greater reliability.

Abstract: A power-saving method of continuous display and effective cost in a system that includes memory directly accessed by a CPU and at least one display device within vertical blanking. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process.

Abstract: A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit, and a trigger current generator. The object of the stacked MOS circuit is to be the first releasing path of the ESD current; the object of the trigger current generator is to generate the trigger current to turn on the stacked MOS circuit, and then the stacked MOS circuit would be the first releasing path of the ESD current.

Abstract: A quantization matrix adjusting method for quality improvement by scaling down the default quantization matrix. The adjusting method comprises the steps of: updating a used bits BB_X and an average quantizer scale Avg_Q; allocating a bit budget BB_C for a current picture; calculating an estimated quantizer scale EstQ_C according to the used bits BB_X, the average quantizer scale Avg_Q and the bit budget BB_C deciding the operation mode, when the estimated quantizer scale EstQ_C is smaller than a threshold Th_Q, assigning the operation mode as an adjusting mode, otherwise remaining at normal mode; scaling down a default quantization matrix as a new quantization matrix when the operation mode is the adjusting mode; and coding the current picture using the new quantization matrix and default quantization matrix in the adjusting mode and normal mode, respectively.

Abstract: A quantization matrix adjusting method for avoiding underflow of VBV by enlarging the default quantization matrix. The adjusting method comprises the steps of: updating a used bits BB_X and an average quantizer scale Avg_Q; allocating the bit budget BB_C for the current picture; calculating an estimated quantizer scale EstQ_C according to the used bits BB_X, the average quantizer scale Avg_Q and the bit budget BB_C; deciding the operation mode, when the estimated quantizer scale EstQ_C is larger than a threshold Th_Q, assigning the operation mode as an alert mode, otherwise remaining at normal mode; enlarging the default quantization matrix as a new quantization matrix when the operation mode is the alert mode; and coding the current picture using the new quantization matrix and default quantization matrix in the alert mode and normal mode, respectively.

Abstract: An apparatus for constant quality rate control in moving picture compression. First, a total activity measure for the current picture to be encoded in a set of consecutive pictures is calculated. Based on the total activity measure of the current picture and an activity-to-complexity ratio of a previously encoded picture of the same type in the set of consecutive pictures, a complexity measure of the current picture is estimated. Thus, an instantaneous complexity measure is updated using the complexity measure and then an instantaneous rate is calculated. A target bit budget is allocated to the current picture depending on the instantaneous rate, the complexity measure and the instantaneous complexity measure. After encoding, the activity-to-complexity ratio for the just encoded picture is computed based on the total activity measure, actual bits consumed by the picture and the average of actual quantization step sizes used to encode the picture.

Abstract: An early retiring instruction mechanism, a method for performing the early retiring instruction mechanism and a pixel processing system employing the early retiring instruction mechanism applied to a graphic processor unit (GPU) are described. The pixel processing system comprises an early retiring instruction mechanism and a pixel shader. The early retiring instruction mechanism selectively retires a plurality of instructions in a first program in order to generate at least one early retiring instruction in a second program. The pixel shader is connected to the early retiring instruction mechanism. The pixel shader fetches the second program and decodes at least one early retiring instruction to execute the second program therein for processing a plurality of pixels. Then, the pixel shader checks whether the pixels in the process of the early retiring instruction generated from early retiring instruction mechanism are directly issued to leave the pixel shader in advance.

Abstract: A method for estimating channels of an OFDM signal. The method comprises the steps of deriving responses of pilot channels, deriving responses of first data channels by time and frequency domain combined linear interpolation among the responses of the pilot channels, deriving each response of boundary channels by frequency domain linear interpolation between the responses of the nearest pilot and first data channels, and deriving responses of second data channels by frequency domain extrapolation using the responses of the pilot and first data channels.

Abstract: A method of mode detection for OFDM signals. The method comprises the steps of delaying the OFDM signal for a first and second number of samples, multiplying the two delayed signals by coefficient signals, and deriving a sum of the two products, deriving an error signal by subtracting the sum of the two products from the OFDM signal, extracting amplitudes of the coefficient signals, and accordingly deriving step size signals, updating the coefficient signals according to the error signal and step size signals, detecting edges of the amplitudes of the coefficient signals, and determining the guard interval length and transmission mode according to the detected edges.

Abstract: This disclosure presents a heat dissipation mechanism, which conducts generated heat of a thermal device to the housing of an electronic apparatus by a metal piece fastened between the thermal device and electronic apparatus, and then dissipates heat into the air through multiple holes opened over an apparatus shell. Besides, the presented mechanism is also suitable to mini-size, portable electronic apparatus to solve the thermal dissipation technique thereof.