Abstract: A metric generation scheme for use in OFDM receivers. In a preferred embodiment, an OFDM receiver of the invention includes a dynamic quantizer to compress a series of channel-state information values. Also, a bit de-interleaver is provided to de-interleave a series of symbol-based data inverse to interleaving operations at a transmitter end. The de-interleaved symbol-based data is further compressed by another dynamic quantizer to yield a complex signal according to a constellation scheme. Then a metric generator calculates a bit metric of a zero group and a bit metric of a one group for each received bit in which the constellation is divided into the one group and the zero group for each bit location.

Abstract: A video encoding method with support for editing when scene changed. The video encoding method reads and stores the pictures by the display order and detects whether the scene change occurred. The method encodes the pictures by the coding order when there are not scenes changed and encodes the pictures by a special coding process when there are scenes changed. Because the video encoding method encodes the pictures with considering the states of scenes changed and generates a new GOP when a scene change occurred, the video sequence can be cut into two parts by an image editing process without re-encoding. Therefore, the video can be edited without any loss and the editing performance of the editing process can be better.

Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit and a trigger current generating circuit. The trigger current generating circuit will generate trigger signal(s) to turn on the stacked MOS circuit under ESD stress condition. The ESD voltage can thus be discharged through the current path formed by the stacked MOS circuit. A lower trigger voltage is achieved by technologies disclosed, which will make an integrated circuit more sensitive to ESD.

Abstract: A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

Abstract: An improved apparatus and method for testing experiment is disclosed. The apparatus includes a motherboard and a stress module. The motherboard includes a component under test. A stress module connects the component and contacts the component directly. The stress module can provide the component with various rages of temperature and voltage for test. Besides, the stress module also can provide an anti-electrostatic device to prevent electrostatic disturbance.

Abstract: An apparatus for variable bit rate control in moving picture compression. First, a total activity measure for the current picture to be encoded in a set of consecutive pictures is calculated. Based on the total activity measure of the current picture and an activity-to-complexity ratio of a previously encoded picture of the same type in the set of consecutive pictures, a complexity measure of the current picture is estimated. A statistical complexity measure is then calculated from the complexity measure of the current picture. A target bit budget is allocated to the current picture depending on the instantaneous rate, the complexity measure and the instantaneous complexity measure. After encoding the current picture, the activity-to-complexity ratio for the current picture is computed based on the total activity measure, actual bits consumed by the current picture and an average of actual quantization step sizes used to encode the current picture.

Abstract: The invention relates to an ESD protection with ability to enhance trigger-on speed of a low voltage Triggered PNP (LVTPNP) unit for protecting internal circuits of an integrated circuit from attack of an ESD stress. The ESD protection unit incorporates either detection circuit or power clamp circuit to efficiently trigger on a trigger node as a heavily doped region of LVTPNP devices among an I/O pad, a VDD pin and a VSS pin. As soon as the trigger node of each LVTPNP device receives a trigger signal from either the ESD detection circuit or power clamp circuit, the threshold voltage of the LVTPNP devices are capable of being therefore reduced to enhance trigger-on speed of the LVTPNP devices that discharge ESD current.

Abstract: A method for motion pixel detection with adaptive thresholds, according to the global motion information among the reference video fields, so as to correctly evaluate whether a missing pixel is in a static region or a non-static region, thereby reconstructing the missing pixel by an inter-field interpolation process or an intra-field interpolation process. If the amount of motion among the reference fields is large, there is high motion information among the reference fields, so the threshold is set to be small; if the amount is small, there is less motion information between the reference fields, and so the threshold should be set to be large.

Abstract: A channel estimator for use in wireless local area networks (WLAN's), characterized in that a channel estimation controller with a simplified recursive least square (RLS) algorithm and a data-reconstructor are employed to adjust the channel response in frequency domain during the delivery of a signal packet. Such adjustment is adaptively performed at anytime during the delivery of a signal packet so as to achieve fast convergence as well as accurate channel estimation.

Abstract: A system for detecting the processing speed of an integrated circuit (IC) includes a flip-flop, a delay module, and a judge unit. The flip-flop receives a clock signal as a trigger signal and generates an inverted output signal. The delay module receives the inverted output signal, adjusts the delay time of the inverted output signal according to a selection signal, and outputs a delay signal to the flip-flop to have the flip-flop generate the output signal. The judge unit receives the output signal and generates a judge signal, which is enabled when the clock period of the output signal is longer than that of the clock signal.

Abstract: An improved apparatus and method for testing experiment is disclosed. The apparatus includes a motherboard and a stress module. The motherboard includes a component under test. A stress module connects the component and contacts the component directly. The stress module can provide the component with various rages of temperature and voltage for test. Besides, the stress module also can provide an anti-electrostatic device to prevent electrostatic disturbance.

Abstract: A frequency offset compensation estimation system and method for a wireless local area network. First, a preamble sequence of a frequency package is sent to a frequency offset estimation (FOE) device so that an initial frequency offset signal amount is obtained and sent to the frequency offset compensation (FOE) device for compensation. Then, the compensated signal is sent to a frequency offset residual phase estimation (FOS RPE) device so as to calculate an offset amount of the frequency and send it to the frequency offset residual phase compensation (FOS RPC) device for compensation. The present invention mainly employs a residual frequency offset estimation device (Residual FOE device) to estimate the residual frequency offset signal of each of the frequency signals compensated by the frequency compensation device and feedback it to the frequency compensation device for compensation.

Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit and a trigger current generating circuit. The trigger current generating circuit will generate trigger signal(s) to turn on the stacked MOS circuit under ESD stress condition. The ESD voltage can thus be discharged through the current path formed by the stacked MOS circuit. A lower trigger voltage is achieved by technologies disclosed, which will make an integrated circuit more sensitive to ESD.

Abstract: A socket base adaptable to a load board for testing semiconductor devices is disclosed. The socket base includes a first fixing element having coupling plates, a probe element, and a second fixing element, which are detachable and combinable. Accordingly, the procedure for replacing the probe element is simplified, time is reduced, and efficiency is increased.

Abstract: The invention relates to a method for detecting video frame types with median filtering, which proceeds a denoising step after calculating the comb factor of each pixel, to avoid incorrect judgment of the frame type resulting from excessive field difference and improve detection accuracy.

Abstract: A residual frequency offset (RFO) compensation method and a compensation system of a multi-carrier communication system is disclosed. The compensatory method of present invention includes two phase-computation steps. The first phase-computation step processes a phase variation of an OFDM data symbol each time to obtain a RFO estimation for compensating a demodulation carrier. The second-phase computation processes a plurality of OFDM data symbols each time to obtain a RFO estimation for compensating the demodulation carrier.

Abstract: A method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board includes utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned in a center area of the die; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of first-layer traces being routed in a first layer of the multi-layer circuit board; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of second-layer traces being routed in a second layer of the multi-layer circuit board; routing the plurality of first-layer traces straight away from the die; and routing the plurality of second-layer traces with a turn not to be vertically underneath the first-layer traces.

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.

Abstract: A Power-saving method, which is able to configure not only the CPU but also the other computer devices, such as the host bus, GUI engine, South Bridge control engine . . . etc., into Power-saving state, has been proposed. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the d display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process. The Power-saving related flag may be built-in North Bridge, South Bridge or CPU.

Abstract: An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal.