Abstract: An apparatus includes a radio-frequency (RF) circuit, which includes a power amplifier coupled to receive an RF input signal and to provide an RF output signal in response to a modified bias signal. The RF circuit further includes a bias path circuit coupled to modify a bias signal as a function of a characteristic of an input signal to generate the modified bias signal. The bias path circuit provides the modified bias signal to the power amplifier.

Abstract: A system and method of recording and transmitting compressed audio signals over a network is disclosed. The end node device first converts the audio signal to a spectrogram, which is commonly used by machine learning algorithms to perform speech recognition. The end node device then compresses the spectrogram prior to transmission. In certain embodiments, the compression is performed using Discrete Cosine Transforms (DCT). Furthermore, in some embodiments, the DCT is performed on the difference between two columns of the spectrogram. Further, in some embodiments, a function that replaces values below a predetermined threshold with zeroes in the Encoded Spectrogram is utilized. These functions may be performed in hardware or software.

Abstract: A test system for testing RF PCBs including an RF probe for interfacing an intermediate node of each RF PCB, an RF source providing an RF test signal, a reflectometer, and a test measurement system that makes a pass/fail determination of each RF PCB using a measured reflection coefficient. Each RF PCB includes an IC matching circuit and an antenna matching circuit coupled between an RFIC and an antenna, in which the intermediate RF node is between the matching circuits. The reflectometer outputs a measured reflection coefficient indicative of a comparison between a reflected RF signal and the RF test signal. The measured reflection coefficient may be corrected using error values based on a calibration procedure using a calibration kit with modified RF PCBs with known loads. The modified RF PCBs are measured with a network analyzer and the test system to calculate the error values used for production testing.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

Abstract: A memory system including a memory device, cache controller circuitry, and timing circuitry. The memory device has a read enable input for receiving a read enable indication for requesting stored data, and has a minimum delay specification between consecutive read enable indications. The cache controller circuitry provides a read indication during a prefetch mode to read data from a next linear address from the memory device, provides a reading indication while data is being read, and provides a miss indication when a next processor address is not the next linear address. The timing circuitry includes synchronization circuitry receiving the read indication and a clock signal and provides a preliminary read enable indication, read enable circuitry receiving a mask indication and the preliminary read enable indication and providing the read enable indication, and mask circuitry that provides the mask indication when the reading indication and the miss indication are both provided.

Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

Abstract: In one form, a software system includes a first non-transitory computer readable medium storing a source code program, a second computer readable medium, and a compiler. The first non-transitory computer readable medium includes a first function having a return type greater than a native width of a target processor, and a second function that calls the first function and that conditionally branches based on comparing a returned value from the first function to an expected value, wherein the expected value has first and second portions that are not equal to zero and are not equal to each other. The compiler converts the source code program in the first non-transitory computer readable medium into a machine language program for storage in the second computer readable medium. The compiler optimizes the source code program by selectively combining a set of redundant machine language instructions into a smaller set of machine language instructions.

Abstract: In one embodiment, an apparatus includes: a digital baseband circuit to receive a digital baseband signal and output a first digital baseband signal and a second digital baseband signal, the second digital baseband signal comprising a scaled version of the first digital baseband signal; a first transmitter signal path coupled to the digital baseband circuit to process the first digital baseband signal and output a first radio frequency (RF) signal; a second transmitter signal path coupled to the digital baseband circuit to process the second digital baseband signal and output a second RF signal; a first power amplifier coupled to the first transmitter signal path to amplify the first RF signal and output an amplified first RF signal; and a second power amplifier coupled to the second transmitter signal path to amplify the second RF signal and output an amplified second RF signal.

Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.

Abstract: A system and method of minimizing interference and retries in an environment where two or more network protocols utilize the same frequency spectrum is disclosed. A lower-power network controller is co-located with a WIFI controller. The lower-power network controller listens for a signature that may indicate the presence of a low power protocol packet, such as BLE or Zigbee. The lower-power controller checks for a waveform that is representative of a Zigbee packet prior to generating a request signal to the WIFI controller. This maximizes the likelihood that no WIFI traffic will occur while the incoming packet is being received.

Abstract: An apparatus includes a radio frequency (RF) receiver. The RF receiver includes a timing correlator and frequency offset estimator. The timing correlator and frequency offset estimator: (a) extracts timing from a set of samples derived from an RF signal, and (b) determines a frequency offset estimate from the set of samples.

Abstract: An apparatus includes a power management circuit to receive an input voltage and to generate and provide a first output voltage to an energy storage device. The power management circuit further generates and provides a second output voltage to a load. The first output voltage is greater than the input voltage, and the second output voltage is smaller than the first output voltage. The apparatus further includes a monitor circuit to monitor the first output voltage and to provide a signal to the load to indicate when the load may perform an operation.

Abstract: A system and method for determining a direction of arrival of an incoming signal is disclosed. The present system utilizes a plurality of pseudo-spectrums to create a more accurate result matrix. The pseudo-spectrums are one or two dimensional arrays, where peaks in the arrays are indicative of the angle of arrival. A result matrix is generated by performing a mathematical operation of corresponding elements in each pseudo-spectrum. This mathematical operation may be addition or multiplication. The result matrix provides a more accurate indication of the angle of arrival than can otherwise by achieved. In some embodiments, a measure of quality may also be calculated for the result matrix.

Abstract: A system and method for detecting and receiving Z-Wave Beams that are transmitted over a plurality of channels is disclosed. The system includes a radio circuit, which includes a Digital Signal Arrival (DSA) circuit and a read channel. The DSA circuit is able to detect the presence of a valid signal on a particular channel, based on received signal power, detected frequency deviation, the magnitude of phase spikes and/or other characteristics. The read channel is able to decode incoming packets. Software is used to control the DSA circuit and the read channel so that, during each wake up period, the FLiRS device monitors all available channels to determine if a Z-Wave Beam is present. If a Z-Wave Beam is detected, the read channel receives the Z-Wave Beam. Otherwise, the FLiRS device returns to sleep mode.

Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.

Abstract: An integrated circuit includes a first plurality of circuits receiving a first internal power supply voltage, a first regulator receiving an external power supply voltage and supplying the first internal power supply voltage at a first rated power in response to the external power supply voltage when the integrated circuit is in an active mode, a second regulator receiving the external power supply voltage for supplying the first internal power supply voltage at a second rated power less than said first rated power in response to the external power supply voltage when the integrated circuit is in a low power mode, and a controller controlling a transition of the integrated circuit between the active mode and the low power mode. The controller activates all of the first plurality of circuits in the active mode, but only a subset of them while keeping remaining ones inactive in the low power mode.

Abstract: A data producer stores input data in a buffer in response to a slow clock signal and provides read data from the buffer in response to a read pointer signal. A data movement circuit reads the input data from the buffer using the read pointer signal and provides an update read pointer signal in response to reading the input data. The data movement circuit operates in response to a fast clock signal, and includes a metastable-free synchronizer circuit having inputs for receiving the update read pointer signal, the slow clock signal, and the read pointer signal, and an output for providing a synchronized read pointer signal equal to the read pointer signal except between a change in the read pointer signal while the slow clock signal is active until an inactivation of the slow clock signal. The buffer provides the read data in response to the synchronized read pointer signal.

Abstract: An IoT device has a public device identifier and a private device identifier, where the public device identifier is publicly available and the private device identifier is secret but kept in a secure device database as a correspondence. A registration request is sent from the IoT device to an association server in communication with the device database having an association between IoT public identifier and a corresponding IoT private identifier. The association server which receives the registration request responds with a registration acknowledgement containing, in encrypted form, the private device identifier of the original request and, optionally, the public device identifier associated with the registration request. The requesting IoT device receives the association acknowledgement, decrypts the private device identifier, compares it to its own device identifier, and if they match, sends one or more association requests.

Abstract: In one aspect, an apparatus includes: a buffer to store orthogonal frequency division multiplexing (OFDM) samples of one or more OFDM symbols; a fast Fourier transform (FFT) engine coupled to the buffer, the FFT engine to receive the one or more OFDM samples from the buffer and convert each of the one or more OFDM samples into a plurality of frequency domain sub-carriers; and a timing control circuit coupled to the buffer. The timing control circuit may control timing based at least in part on a difference between a first correlation sum for a first portion of a cyclic prefix of a first one of the one or more OFDM symbols and a second correlation sum for a second portion of the cyclic prefix.