Abstract: A sine to square wave converter circuit receives a sine wave signal and supplies a first square wave signal having a first frequency. A 2× clock multiplier circuit multiplies the first square wave signal and supplies a second square wave signal with a second frequency that is twice the first frequency. A first storage element that is clocked by the second square wave signal stores a delayed version of the first square wave signal and supplies an even-odd signal. A second storage element that is clocked by the second square wave signal receives the even-odd signal and supplies an odd-even signal. A duty cycle correction circuit adjusts the threshold of the sine to square wave converter based on a difference in duty pulse widths between the even-odd signal and the odd-even signal.

Abstract: A receiver signal path includes a high pass filter that centers a received differential pair of signals around a common mode voltage to generate a centered received differential pair of signals. The receiver signal path includes a demodulator that removes a carrier signal from the centered received differential pair of signals to generate a demodulated signal and generates a logic signal based on the demodulated signal and a predetermined threshold signal. The demodulator includes a differential stage including an extremum selector circuit that generates the demodulated signal based on the centered received differential pair of signals. The demodulated signal corresponds to a mean level of the rectified version of the centered received differential pair of signals. The differential stage includes a second circuit that provides the reference signal based on the predetermined threshold signal. The logic signal is based on a comparison of the demodulated signal to the reference signal.

Abstract: A technique for receiving a DC or low frequency input signal using a chopper-stabilized amplifier includes chopping an input signal using a chopper clock signal to generate a chopped input signal. The input signal has a first voltage range and the chopper clock signal has a second voltage range. The chopper clock signal has peak-to-peak voltage over a period of the chopper clock signal. The peak-to-peak voltage is less than the first voltage range and is less than the second voltage range. A frequency of the input signal is at least an order of magnitude less than a frequency of the chopper clock signal. The second voltage range may be greater than or equal to the first voltage range. The technique may include generating a bias signal based on a voltage reference signal and an output signal having the first voltage range.

Abstract: A receiver signal path includes a programmable flat gain stage configured to provide an amplified differential pair of signals based on a first frequency response having a selectable flat gain and a differential input pair of signals received on an input differential pair of nodes. The receiver signal path includes a peaking gain stage configured to generate a second amplified differential pair of signals based on the amplified differential pair of signals according to a second frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency of the peaking gain stage. The programmable flat gain stage and the peaking gain stage are configured as a variable peaking gain stage. The selectable flat gain is selectively programmed based on a predetermined power consumption of a receiver path.

Abstract: In one example, a remote tuner module includes: a first tuner to receive, process and demodulate a first radio frequency (RF) signal to output an analog audio signal, and to receive and process a second RF signal to output a first downconverted modulated signal; a second tuner to receive and process the second RF signal to output a second downconverted modulated signal; a demodulator circuit coupled to the first and second tuners to demodulate and link the first and second modulated signals, to output a linked demodulated signal. The remote tuner module may further include a gateway circuit coupled to at least the demodulator circuit to output the analog audio signal and the linked demodulated signal.

Abstract: An apparatus includes a radio frequency (RF) circuit to transmit or receive RF signals, and a partitioned antenna structure. The partitioned antenna structure includes a first portion of a resonator and a first portion of a radiator. The first portion of the resonator comprises less than an entire resonator. The first portion of the radiator comprises less than an entire radiator.

Abstract: A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibration signal based on the digital phase error signal.

Abstract: A power transfer device includes a first power supply node, a second power supply node, and an oscillator circuit configured to convert an input DC signal across the first power supply node and the second power supply node into an AC signal on a differential pair of nodes comprising a first node and a second node in response to a control signal. The oscillator circuit includes a regulated power supply node and an active shunt regulator circuit configured to clamp a peak voltage level across the regulated power supply node and the second power supply node to a clamped voltage level. The clamped voltage level is linearly related to a first voltage level on the first power supply node.

Abstract: A digital to analog converter that includes a delta sigma modulator coupled to receive a digital data. The delta sigma modulator supplies a multi-bit resistor digital to analog converter (DAC). The multi-bit resistor digital to analog converter supplies an amplifier with an analog signal corresponding to the digital data. A first low pass filter is coupled between the multi-bit digital to analog converter and the amplifier stage and filters out shaped quantization noise before it reaches the amplifier. A second low pass filter is coupled to an output of the amplifier stage and filters out residual quantization noise and chopping artifacts from the amplifier stage.

Abstract: In an embodiment, an apparatus includes: a modulator to modulate a first packet according to rate control information; a physical circuit to transmit the modulated first packet according to power control information; and a dynamic adaptation circuit, for the first packet, to provide the rate control information and the power control information of a first modulation and power pair stored in a first energy map.

Abstract: An apparatus includes a time-to-digital converter (TDC). The TDC includes a fine TDC (F-TDC) to generate a first output signal in a first range in response to a first signal and a second signal, and a coarse TDC (C-TDC) to generate a second output signal in a second range in response to the first signal and a delayed version of the second signal.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: A system and method for efficiently creating multicast groups is disclosed. The system includes a gateway controller, that receives a multicast request from a client. The gateway controller parses the request from the client and identifies the set of the desired destination nodes. The gateway controller then determines whether an existing multicast group matches this set. If not, the gateway controller creates a new multicast group, preferably by modifying an existing multicast group by adding new destination nodes to that group. This is an efficient way to create multicast groups, as it increases the number of nodes reacting simultaneously to multicast messages when creating multicast groups, and minimizes the number of messages that are required to synchronize the nodes to the new multicast group.

Abstract: In one aspect, a method includes: iteratively, for each of a plurality of code maps each formed based on one of a plurality of base spreading codes: determining, in a computing system, a plurality of metrics for the code map; and computing, in the computing system, a weighted sum for the code map based on at least some of the plurality of metrics. After this iterative operation, a first base spreading code associated with the weighted sum having an optimal value may be selected. This first base spreading code may be used to configure one or more wireless devices with the first base spreading code to cause the one or more wireless devices to communicate coded symbols using the first base spreading code.

Abstract: A clock product includes a phase-locked loop configured to generate an output clock signal based on an input digital value and a feedback digital value. The input digital value corresponds to a first clock edge of a frequency-divided input clock signal and the feedback digital value corresponds to a second clock edge of a feedback clock signal. The clock product includes an input fractional divider configured to generate the input digital value based on an input clock signal, a divider value, and an input clock period digital code corresponding to a period of the input clock signal.

Abstract: A calibration operation adjusts a frequency of a ring oscillator to a desired frequency by adjusting programmable RC circuits in the stages of the ring oscillator. The programmable RC circuits have programmable capacitors, resistors, or both. The RC circuits account for most of the delay through the ring oscillator. Another circuit with its own RC time constant is calibrated based on the adjustments made to the RC circuits in the ring oscillator to achieve the desired frequency.

Abstract: The present invention relates to a method and system of locating a wireless device using received signal strengths. The method comprising: determining a plurality of multiple sets of transmit beamforming weights corresponding to a plurality of access points (APs) associated with a plurality of time slots; transmitting a signal using said each of said plurality of multiple sets of transmit beamforming weights associated with said plurality of time slots by said each access point (AP) of said plurality of access points (APs); and generating a plurality of received signal strengths corresponding to said plurality of time slots associated with said each of said plurality of multiple sets of transmit beamforming weights by said each access point (AP) of said plurality of access points (APs) at any location.

Abstract: In an embodiment, an integrated circuit includes: a switched capacitor coupled between a supply voltage node and a divider node, where a thermistor external to the integrated circuit is to couple to the divider node; an analog-to-digital converter (ADC) coupled to the divider node to receive a voltage at the divider node and generate a digital value based thereon; and a controller coupled to the ADC to determine a temperature associated with the thermistor based at least in part on the digital value.

Abstract: A power transfer device includes an oscillator circuit of a DC/AC power converter responsive to an input DC signal and an oscillator enable signal to generate an AC signal. The oscillator circuit includes a first node, a second node, and a circuit coupled between the first node and the second node. The circuit includes a cross-coupled pair of devices. The oscillator circuit further includes a variable capacitor coupled between the first node and the second node. A capacitance of the variable capacitor is based on a digital control signal. A first frequency of a pseudo-differential signal on the first node and the second node is based on the capacitance. The power transfer device further includes a control circuit configured to periodically update the digital control signal. A second frequency of periodic updates to the digital control signal is different from the first frequency.

Abstract: A power saving wire-free earpiece has a Bluetooth transceiver and a Bluetooth Low Energy (BLE) transceiver. A stream of audio from a remote source is separated into a local audio stream and a stream sent to the BLE transceiver for a remote earpiece. The earpiece is operative in a first and second mode, the first mode enabling the BT transceiver and BLE transceiver, the second mode enabling only the BLE transceiver for receiving remote streams of data. The first and second mode alternate so that the local and remote earpiece have substantially uniform current requirements.