Abstract: In one embodiment, an apparatus includes a clock generator circuit to receive a first clock signal at a first frequency and output a second clock signal at a second frequency less than the first clock frequency. The clock generator circuit may include: a divider circuit to divide the first clock signal to obtain at least a first divided clock signal and a second divided clock signal; and a gating circuit coupled to the divider circuit, the gating circuit to gate the first clock signal with at least one of the first divided clock signal and the second divided clock signal to output the second clock signal.

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

Abstract: A wireless device may include: a radio frequency (RF) front end circuit to receive and process an RF signal; a mixer to downconvert the RF signal to a second frequency signal; a digitizer to digitize the second frequency signal; a channel filter to channel filter the digitized signal; a selection circuit having a first input coupled to the channel filter and a plurality of outputs each to couple to one of a plurality of demodulators; and the plurality of demodulators coupled to the selection circuit. The selection circuit may route the channel filtered digitized signal to a first demodulator of the plurality of demodulators based on a first configuration setting. The wireless device may also include a non-volatile storage with a configuration file including the first configuration setting. The configuration file may be automatically generated by a hardware configurator in response to a plurality of user input parameters.

Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

Abstract: An apparatus includes a power management circuit to receive an input voltage and to generate and provide a first output voltage to an energy storage device. The power management circuit further generates and provides a second output voltage to a load. The first output voltage is greater than the input voltage, and the second output voltage is smaller than the first output voltage. The apparatus further includes a monitor circuit to monitor the first output voltage and to provide a signal to the load to indicate when the load may perform an operation.

Abstract: A receiver includes a first discrete Fourier transform (DFT) block to perform a first single tone DFT on a positive tone associated with a sounding sequence. A second DFT block performs a second single tone DFT on a negative tone associated with the sounding sequence. A DFT coefficient generation block generates first DFT coefficients based on a nominal frequency of the positive tone and an estimated frequency offset between a transmitter frequency and a receiver frequency. The DFT coefficient generation block generates second DFT coefficients based on a nominal frequency of the negative tone and the estimated frequency offset. Multipliers in the DFT blocks multiply I and Q values of the sounding sequence with the coefficients. Accumulators in the DFT blocks accumulate multiplier outputs. An arctan function receives averaged accumulated values from the first and second DFT blocks and supplies first and second phase values used to calculate fractional timing.

Abstract: A system and method for detecting a multipath environment is disclosed. A first pseudospectrum based on azimuth angle and elevation angle is created. The result of this first pseudospectrum are used to create a second pseudospectrum based on polarization and field ratio. The sharpness of the results for these two pseudospectrums is determined and may be used to detect whether a multipath environment exists. If a multipath environment is believed to exist, the results from this device are ignored in determining the spatial position of the object.

Abstract: A system and method for embedding a tool into an Integrated Development Environment (IDE) is disclosed. The system includes a special application programming interface (API) that is used to embed any tool into any IDE. The API provides a way for the tool to indicate what functions are supported by the tool. These functions may include save, print, edit and others. The API also provides a mechanism for the IDE to communicate to the tool that one of the supported functions is to be executed. Finally, the API provides a mechanism for the tool to report information to the IDE as necessary.

Abstract: A receiver for OFDM subcarriers has a first mode and a second mode. In the first mode, a tunable system clock is output at a nominal frequency, and in the second mode, the tunable system clock is offset so that a harmonic of the tunable system clock coincides with a particular OFDM subcarrier. The tunable system clock is coupled to a programmable modem PLL clock generator which generates clocks for an A/D converter coupled to a baseband processor which is also coupled to the programmable modem PLL clock generator. The programmable modem PLL clock generator is programmed to maintain a constant output frequency of each output in the first mode and the second mode.

Abstract: In one aspect, a radio device comprises: an analog front end (AFE) circuit to receive and process an incoming radio frequency (RF) signal comprising a packet; an analog-to-digital converter (ADC) coupled to the AFE circuit to receive and digitize the processed incoming RF signal into a digital signal; a detector coupled to the ADC to detect a carrier frequency offset (CFO) in the digital signal based at least in part on a preamble of the packet; and a controller coupled to the detector. The controller may generate a compensation value for the CFO based on the detected CFO and cause one or more components of the radio device to compensate for the CFO using the compensation value.

Abstract: A wireless local area network (WLAN) station receiver has a center frequency offset (CFO) estimator and an CFO table with an association between a CFO value from a recently received access point packet for which the station is associated according to 802.11. The receiver performs a comparison between the CFO estimate of the received packet and the CFO value from the CFO database, and powers the receiver down if the comparison exceeds a threshold. The threshold may be an absolute value in parts per million, or may include a time drift compensation component.

Abstract: An integrated circuit includes a capacitor with a bottom conductive plate and a top conductive plate. A passivation layer is disposed above the top conductive plate. An intermetal dielectric layer is disposed between the bottom conductive plate and the top conductive plate and is formed of a first dielectric material. Shield layers are disposed between the top conductive plate and above the intermetal dielectric layer and extend horizontally to at least past guard rings. The shield layers include a dielectric layer formed of dielectric material having a dielectric constant greater than the material of the intermetal dielectric layer. The shield layers include horizontally offset trenches to stop horizontal flow of current in the shield layers. The offset ensures there is no vertical path from the passivation layer to lower/ground potentials through the shield layers.

Abstract: A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

Abstract: A system and method for detecting the presence of a Bluetooth or Zigbee signal within a short period of time is disclosed. The signal identification circuit has two stages, a first stage that processes windows to determine whether noise is present, and a second stage that processes long windows to determine whether the signal is a particular lower-power network protocol. The signal identification circuit can be configured to detect Bluetooth at 1 Mbps, Bluetooth at 2 Mbps or Zigbee. The signal identification signal may be used to allow a lower-power network controller to coexist with a high duty cycle WiFi controller. The signal identification circuit may also be used for other functions, such as powering on a lower-power network controller, determining CCA, or determining which channel a packet is being transmitted on.

Abstract: An apparatus comprises an RF receiver for receiving an RF signal. The RF receiver includes front-end circuitry to generate a first down-converted signal, and a plurality of signal detectors to generate a corresponding plurality of detection signals from signals derived from the down-converted signal. The RF receiver further includes a controller to provide at least one control signal to the front-end circuitry based on the plurality of detection signals.

Abstract: An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. Furthermore, this new antenna array also requires less space than conventional antenna arrays.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: In one embodiment, an apparatus includes: a radio frequency (RF) front end circuit to receive and downconvert a RF signal to a second frequency signal, the RF signal comprising an orthogonal frequency division multiplexing (OFDM) transmission; a digitizer coupled to the RF front end circuit to digitize the second frequency signal to a digital signal; and a baseband processor coupled to the digitizer to process the digital signal. The baseband circuit comprises a first circuit having a first plurality of correlators having an irregular comb structure, each of the first plurality of correlators associated with a carrier frequency offset and to calculate a first correlation on a first portion of a preamble of the OFDM transmission.

Abstract: An integrated circuit including an input terminal and an output terminal, signal generator circuitry that generates a pseudo-random digital signal provided at the output terminal, and comparator circuitry that compares an input signal received via the input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof. The signal generator circuitry may be a pseudo-random binary sequence generator or may be a linear-feedback shift register with software triggered reloading. The comparator circuitry may include a Boolean logic exclusive-OR gate for comparing the output and input signals. A method of detecting tampering including generating and providing a pseudo-random digital signal at an output terminal and comparing an input signal received via an input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof.

Abstract: A system and method for performing discrete frequency transform including a pair of single-bit analog to digital converters (ADCs), a phase converter, a memory, a discrete frequency transform converter and summation circuitry. The ADCs convert an analog input signal into N pairs of binary in-phase and quadrature component samples each being one of four values at a corresponding one of four phases. The phase converter determines a phase value for each pair of component samples. The memory stores a set of discrete frequency transform coefficient values based on N. The discrete frequency transform converter uses a phase value and a pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a discrete frequency component for each pair of phase component samples. The summation circuitry sums the corresponding N frequency domain components for determining a frequency domain value for the selected frequency bin.