Patents Assigned to Silicon Laboratories
  • Patent number: 12031873
    Abstract: A temperature sensor that is insensitive to process variation and mismatch is disclosed. The temperature sensor includes a PTAT voltage generator, a sampling and gain boosting circuit, a filter and a controller. The PTAT voltage generator utilizes a plurality of current sources, each of which is in electrical communication with the same diode, or diode stack. The output of the PTAT voltage generator is sampled and amplified with the sampling and gain boosting circuit. The output of the sampling and gain boosting circuit is then filtered using a low pass filter. The selection of the current mirrors, the sampling timing and other signals are provided by the controller. In some simulations, the output from the temperature sensor was accurate to within 1.5° C., using a one temperature calibration process.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: July 9, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Peh Sheng Jue, Jeffrey L. Sonntag
  • Patent number: 12035152
    Abstract: A software system for use with a network controller is disclosed. The software system comprises a plurality of modules, wherein some of the modules are specific to the network protocol used by the network controller. Other modules are usable for a variety of network protocols without modification. In this way, the development of the software for a network controller may be simplified resulting in less development time. Further, this system allows for flexibility to add attributes and rules at any time without modification to most of the system. The software system includes an attribute store, a resolver engine, a frame handler, a frame transmitter and a frame receiver.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: July 9, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Anders Lynge Esbensen, Nicolas Obriot, Dereje Assefa Wassie, An-ta Huang
  • Patent number: 12034831
    Abstract: A system and method of performing an AES encryption, while also determining whether a potentially successful DFA attack is underway is disclosed. When interim results are not visible, the DFA attack that is most likely to be succeed is initiated by introducing the fault between the MixColumns operation in the second to last round and the MixColumns operation in the next to last round. To detect this, the present system and method performs the next to last round and then repeats this next to last round. The results of the original round and repeated round are compared to identify a possible DFA attack. Importantly, the same hardware is used for the original round and the repeated round. In this way, the amount of additional hardware needed to detect a possibly successful DFA attack is minimized. Further, the impact on execution time may be 10% or less.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: July 9, 2024
    Assignee: Silicon Laboratories Inc.
    Inventor: Steven Cooreman
  • Patent number: 12034551
    Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: July 9, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Partha Sarathy Murali, Ajay Mantha, Nagaraj Reddy Anakala, Subba Reddy Kallam, Venkat Mattela
  • Patent number: 12028024
    Abstract: A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to use the delayed oscillating signal for transmitting a signal, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: July 2, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Rangakrishnan Srinivasan, Mustafa H. Koroglu, Zhongda Wang, Francesco Barale, Abdulkerim L Coban, John M. Khoury, Sriharsha Vasadi, Michael S. Johnson, Vitor Pereira
  • Patent number: 12028444
    Abstract: An ultra low power network device is disclosed. The network device utilizes a Near Field Communications (NFC) tag to enable ultra low power communications with a configuration tool. The configuration tool writes information to the NFC tag that is accessible by the processing unit on the ultra low power network device. Additionally, the processing unit can write information into the NFC tag that is readable by the configuration tool. By exchanging messaged in this manner, the ultra low power network device and the configuration tool may create a shared encryption key. The ultra low power network device utilizes this shared encryption key when transmitting BLUETOOTH® packets. The configuration tool may then transmit the shared encryption key to either another BLUETOOTH® device or to a remote server. The ultra low power network device may also periodically refresh the shared encryption key.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: July 2, 2024
    Assignee: Silicon Laboratories Inc.
    Inventor: Hannu Mallat
  • Patent number: 12028743
    Abstract: In an embodiment, a gateway includes: a radio circuit having a plurality of wireless protocol circuits, each to communicate wirelessly with one or more nodes present in a wireless network; an interface circuit to couple to one or more cloud-based devices via another network; and a controller coupled to the interface circuit. The controller may include a control circuit to control the wireless network, where in response to detection of an active user interface for the wireless network, the control circuit may dynamically update a status report messaging level of at least some of a plurality of nodes present in the wireless network.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 2, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Peter Shorty, Esben Østergård
  • Patent number: 12019124
    Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: June 25, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey L. Sonntag, Timothy J. Dupuis, Jinwen Xiao
  • Patent number: 12015343
    Abstract: In one embodiment, a method includes: enabling a pulse pair circuit of an integrated circuit in response to determining that a receiver associated with the integrated circuit is active; identifying that at least one comparator of a multi-output DC-DC converter trips, the DC-DC converter having a plurality of comparators each to compare a regulated voltage output by the DC-DC converter to a corresponding reference voltage; and generating, in the pulse pair circuit, a control pulse pair according to the tripped output, and driving a driver circuit of the DC-DC converter using the control pulse pair.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: June 18, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Hatem Osman, Michael D. Mulligan, Mohamed Elkholy
  • Patent number: 12009597
    Abstract: An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. A ground skirt surrounds the perimeter of the antenna array to improve radiation phase pattern balance within the array.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: June 11, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Attila Zólomy, Ádám Süle, Daniel Simon, Kiruba Sankaran Subramani, Terry Lee Dickey, Jeffrey Tindle
  • Patent number: 12009793
    Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: June 11, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Ruifeng Sun, Sherry Wu, Michael S. Johnson, Vitor Pereira
  • Patent number: 11995007
    Abstract: A multi-bus protocol memory controller is disclosed. The memory controller utilizes shim circuits to translate between the various bus protocols used in the System on a Chip (SoC) and the bus protocol used by the memory controller. The use of shim circuits reduces the number of bridges required in the SoC and also increases performance. The memory controller is designed such that it may interface with any bus protocol, requiring only the design and inclusion of a shim circuit for that bus protocol.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: May 28, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Paul Ivan Zavalney, Rejoy Roy Mathews
  • Patent number: 11984866
    Abstract: A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: May 14, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Vitor Pereira, Jeffrey A. Tindle, Mustafa H. Koroglu, Terry Lee Dickey
  • Patent number: 11982710
    Abstract: In one embodiment, a method includes: powering on an integrated circuit (IC) and causing the IC to enter into a reset mode, where in the reset mode, a switch coupled between an oscillator of the IC and a reset pin is open; releasing the reset pin to cause the IC to enter into a non-reset mode, where in the non-reset mode the switch is closed to cause the clock signal to be superimposed on a reset signal at the reset pin; and determining, via a monitoring circuit coupled to the IC, the IC as functional in response to identifying the clock signal superimposed on the reset signal at the reset pin.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: May 14, 2024
    Assignee: Silicon Laboratories Inc.
    Inventor: Eugenio Carey
  • Patent number: 11978962
    Abstract: An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. Furthermore, this new antenna array also requires less space than conventional antenna arrays.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: May 7, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Attila Zólomy, Ádám Süle, Joel Kauppo, Terry Lee Dickey, Jeffrey Tindle
  • Patent number: 11979846
    Abstract: A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by disposing the divider outside the phase locked loop and using the output of the divider to create the clocks for both the transmit circuit and receive circuit. In another embodiment, one or more dividers are disposed outside the phase locked loop, each having a reset, such that they can be initialized to a predetermined state. Further, by utilizing a divider with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: May 7, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Rangakrishnan Srinivasan, John Khoury
  • Patent number: 11973509
    Abstract: A phase-locked loop (PLL) that provides a local oscillator signal for a radio. An oscillator of the PLL supplies an oscillator output signal. Control logic receives a request to change the oscillator output signal to a new frequency and responds to the request by setting a first capacitor circuit of the oscillator to a first capacitance that corresponds to a predetermined frequency of the oscillator output signal. The control logic also responds to the request by setting one or more other capacitor circuits of the oscillator according to temperature and according to a frequency difference between the predetermined frequency and the new frequency. After responding to the request by setting the first capacitor circuit and the one or more other capacitor circuits, the PLL locks to the new frequency using a signal from the PLL loop filter to adjust another capacitor circuit in the oscillator.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: April 30, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Rangakrishnan Srinivasan, Zhongda Wang, Francesco Barale, Wenhuan Yu, Mustafa H. Koroglu, Yan Zhou, Terry L. Dickey
  • Patent number: 11973481
    Abstract: A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: April 30, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Vitor Pereira, Jeffrey A. Tindle, Mustafa H. Koroglu, Terry Lee Dickey
  • Patent number: 11963037
    Abstract: A wireless locator that facilitates determining a location of a nearby wireless asset including an antenna array with multiple antennas, at least one wireless transceiver that receives a location signal from the nearby wireless asset and that takes multiple samples from the location signal including a set of samples for each antenna, and a processor that compresses the samples to generate location information associated with the nearby wireless asset. The wireless locator may be part of a wireless location system including multiple wireless locators distributed in the area and a central processing system. Various compression methods are disclosed, including averaging of the samples, bit reduction of the samples, converting the samples to corresponding phase values, and combining corresponding samples of multiple sample supplemental sets. Combinations of the various compression methods are also disclosed.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 16, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Antonio Torrini, Joel Kauppo, Sauli Johannes Lehtimaki
  • Patent number: 11962325
    Abstract: A system and method for detecting the preamble of a wireless packet is disclosed. The system utilizes one or more received fragments as inputs to a correlator, forming correlator content inside the correlator memory. After every sample from the received fragment is provided to the correlator, the correlator then compares the correlator content to a known pattern pre-programmed as a set of correlation coefficients. The correlation coefficients may not align with the correlator content because the symbol boundaries are not known a-priori. By cyclic rotation of the correlation coefficients relative to the correlator content, or cyclic rotation of the correlator content relative to the known correlation coefficients, a match with one or more preamble symbols may be found. This technique may be used to reduce power during the preamble detection process. Alternatively, this technique can also be used for antenna diversity, multi PHY and multichannel applications.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 16, 2024
    Assignee: Silicon Laboratories Inc.
    Inventor: Hendricus de Ruijter