Abstract: An apparatus includes an input terminal to receive a radio frequency (RF) signal and to communicate the RF signal to a low noise amplifier (LNA) via an input signal path, and a capacitor attenuator coupled to the input terminal to attenuate the RF signal by a controllable amount and having a first portion controllable to include a used part configured on the input signal path and an unused part coupled between the input signal path and an AC reference node, and a second portion coupled between the LNA and the AC reference node.

Abstract: An apparatus includes a detector to detect an idle state of a communication link that communicates bursts or packets of information. The apparatus also includes an oscillator having low-power and normal modes of operation. The oscillator makes a transition to the low-power mode during the idle state of the communication link. The oscillator leaves the low-power mode of operation and enters the normal mode of operation when the communication link is in a non-idle state.

Abstract: A circuit includes a controller configured to determine a calibration state of a circuit, to determine an active mode state of the circuit, and to select a type of calibration operation based on the calibration state. The controller is configured to control timing of the selected type of calibration operation in response to determining the calibration state to correspond to a time when the circuit is not active.

Abstract: An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit.

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is lower than the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

Abstract: A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.

Abstract: In one form, an oscillator includes an oscillator core circuit and a dynamic gain control circuit. The oscillator core circuit is for connection to a frequency reference element and provides a first clock signal using a negative gain element having a gain determined by a gain control signal. The dynamic gain control circuit is coupled to the oscillator core circuit for calibrating the gain control signal to a startup value based on oscillations reaching a first threshold during a startup state, and calibrating the gain control signal to a steady-state value based on oscillations falling to a second threshold after an end of the startup state and before entering a steady state. The first threshold is higher than the second threshold. The dynamic gain control circuit operates the oscillator core circuit during the steady state using the steady-state value.

Abstract: A noise-shaping signed digital-to-analog converter is described. A method includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a signed digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The method includes generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the signed digital code. The method may include combining the plurality of analog signals with an output of a phase/frequency detector and charge pump in a phase-locked loop. The signed digital code may be an error signal based on a predetermined divide ratio of the phase-locked loop.

Abstract: A gap detector detects when a phase difference between a feedback signal and a clock signal is larger than a gap threshold. If the phase difference is larger than the gap threshold, then the phase difference is modified by subtracting a gap value from the phase difference. If the phase difference is less than the threshold, the phase difference is not modified. A loop filter receives and filters the modified or unmodified phase difference and controls an oscillator. An accumulator circuit accumulates the modified phase difference and supplies a phase adjust signal. A low pass filter receives the phase adjust signal and supplies a filtered phase adjust signal that is used to slowly adjust the output of the oscillator.

Abstract: A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action.

Abstract: A DC-DC converter includes a plurality of switches configured to be in a first charging mode until current through an inductor reaches a first current threshold to thereby indicate an end of the first charging mode. Responsive to the end of the first charging mode the DC-DC converter is configured to operate in a second charging mode for a time period ?T in which a first side of the inductor is coupled to an input voltage and a second side of the inductor is coupled to a load. Responsive to the end of the time period ?T, the DC-DC converter operates in a discharge mode until current through the inductor reaches its minimum.

Abstract: Systems and methods are provided that may be implemented to improve accuracy of relative humidity (RH) determination from dielectric sensing material-based RH sensors, e.g., by decreasing shift and drift effects and compensating for dielectric material aging to improve RH sensor accuracy. The disclosed systems and methods may be implemented to improve RH sensing accuracy by correcting humidity-sensitive electrical parameters (e.g., capacitance, effective resistance, etc.) based on other other measured sensor electrical operating characteristics (e.g., such as real time sensor circuit phase angle) and/or selection of sensor electrical parameters (e.g., such as optimized operating frequency) that are employed for sensing changes in dielectric constant of a dielectric material-based RH sensor.

Abstract: A low voltage AC power controller uses a line coupled capacitor AC to DC converter circuit to obtain energy from AC line power supplied to an AC load and may be used with an external high voltage AC switching device to control power supplied to the AC load. The line coupled capacitor AC to DC converter circuit provides a low power device that senses characteristics of the power supplied to the load and can communicate sensed information and/or receive control information related to the power supplied to the load.

Abstract: A technique for on-chip time measurement includes dynamically scaling a range of a time-based digital-to-analog converter to enhance resolution of the time measurement. An apparatus includes a first time-based digital-to-analog converter configured to generate a first clock signal based on a first reference clock signal and a first digital code. The apparatus includes a second time-based digital-to-analog converter configured to generate a second clock signal based on a second reference clock signal and a second digital code. The first reference clock signal has a first frequency and the second reference clock signal has a second frequency that is harmonically related to the first frequency. The apparatus includes a time signal converter configured to generate an output signal having a level indicative of a time-of-arrival of a first edge of the first clock signal relative to a time-of-arrival of a second edge of the second clock signal.

Abstract: An apparatus for controlling a high-power drive device external to a package of a motor drive circuit includes a motor drive circuit. The motor drive circuit includes a driver to control the high-power drive device based on a first reference voltage, a second reference voltage, and a control signal based on a received control signal. A fault circuit generates a failure indicator based on a voltage across terminals of the high-power drive device. A fault condition is based on the failure indicator. A first terminal coupled to the driver charges a node of the high-power drive device over a first length of time in response to an absence of the fault condition and a first level of the control signal. A second terminal coupled to the driver discharges the node over a second length of time different from the first length of time.

Abstract: An apparatus includes a sensor circuit to receive a varying signal at an input of the apparatus. The sensor circuit provides a sensor signal corresponding to a measurement of the varying signal. The apparatus further includes a timer circuit to generate a signal at various intervals of a plurality of intervals and a controller coupled to the sensor circuit. The controller has a first power mode and a second power mode, where the first power mode has a lower power consumption than the second power mode. The controller enters the second power mode in response to the signal from the timer circuit. The controller enables the sensor circuit, captures a plurality of measurements of the varying signal, and returns to the first power mode.

Abstract: A technique includes driving a node of a stage of a ring counter to a predetermined signal state; and clocking the ring counter to cause the signal state to propagate to at least one additional stage of the ring counter to initialize the ring counter with a reset sequence.

Abstract: An apparatus includes a multi-stage amplifier. The multi-stage amplifier includes first, second, and third amplifier circuits coupled in a cascade configuration. The multi-stage amplifier further includes first, second, and third compensation networks. The first compensation network is coupled between the output of the third amplifier circuit and the input of the second amplifier circuit. The second compensation network is coupled between the output of the third amplifier circuit and the input of the third amplifier circuit. The third compensation network is coupled between the output of the second amplifier circuit and the input of the second amplifier circuit.

Abstract: In one aspect, a tuner includes an analog front end to receive a radio frequency (RF) signal and to downconvert the RF signal to a second frequency signal, a digitizer to convert the second frequency signal to a digitized signal, a channel equalizer including a filter to filter the digitized signal, and a first controller to update the filter according to a frequency response of the filter.

Abstract: Two sets of information (phase and cycle count) that are created asynchronously in a voltage controlled oscillator based analog-to-digital converter. A third set of information is created that is a delayed cycle count. The three sets of information are used to determine the proper alignment of the phase and the cycle count.