Abstract: An apparatus includes a microelectromechanical system (MEMS) device. The MEMS device includes a resonator suspended from a substrate, an anchor disposed at a center of the resonator, a plurality of suspended beams radiating between the anchor and the resonator, a plurality of first electrodes disposed about the anchor, and a plurality of second electrodes disposed about the anchor. The plurality of first electrodes and the resonator form a first electrostatic transducer. The plurality of second electrodes and the resonator form a second electrostatic transducer. The first electrostatic transducer and the second electrostatic transducer are configured to sustain rotational vibrations of the resonator at a predetermined frequency about an axis through the center of the resonator and orthogonal to a plane of the substrate in response to a signal on the first electrode.

Abstract: A wireless transceiver includes receiver front-end circuitry for processing an ingoing radio frequency (RF) signal to produce an in-going digital signal to a processor connected to receive the in-going digital signal. The processor includes sync word determination logic configured to identify a received sync word or other event or connection point and to subsequently generate an event determination signal. A low power oscillator produces low frequency pulses to a first counter. A crystal oscillator that produces higher frequency pulses to a second counter is used for the last portion of the desired sleep time for greater resolution. Thus, a calibration controller receives pulse counts from at least one of the first and second counters and determines a period between a common event of subsequent beacon signals or connection events and determines wake up times based on the received pulse counts from at least one of the first and second counters.

Abstract: The application relates to a method, an apparatus and a computer program product. The method comprises adjusting dynamically a sensitivity of a receiver from a default sensitivity to a low sensitivity; wherein the adjusting is based on the signal strength of at least one existing connection or at least one previous connection; receiving only such packets by the receiver which are available with the low sensitivity.

Abstract: Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.

Abstract: Diode string configurations are provided that employ one or more guard bars (GBARS) positioned adjacent an end diode structure of a diode string to create a parasitic silicon-controlled rectifier (SCR) coupling between the end diode structure and the guard bar/s that operates to discharge current of an ESD event through a lateral parasitic bipolar transistor of the SCR and away from the individual diodes of the diode string. One or more of the disclosed guard bars may be positioned adjacent to a diode on a first end of a diode string to create a lateral SCR coupling for ESD discharge away from all of the diodes in the diode string without requiring positioning of a last diode on an opposite end of the same diode string adjacent the first terminal diode.

Abstract: Reference signal generators using thermistors are disclosed. An apparatus includes a first device having a first temperature coefficient and a thermistor having a second temperature coefficient having a sign opposite to that of the first temperature coefficient. A circuit maintains equivalence of a first signal and a second signal and offsets a first temperature variation of the first device using a second temperature variation of the thermistor to generate the second signal having a low temperature coefficient. The first device may be a bipolar transistor configured to generate a base-emitter voltage and coupled in series with the thermistor. The first signal may be a first voltage on a first node. The second signal may be a second voltage on a second node. The circuit may be configured to maintain effective equivalence of the first voltage and the second voltage. The apparatus may include a resistor coupled to the second node.

Abstract: In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.

Abstract: A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.

Abstract: A technique includes controlling a modulus of a programmable divider, including selectively activating and deactivating cells of the divider. The activation for at least one of the cells includes configuring an output signal of the cell to exhibit a predetermined signal state when the cell transitions from a deactivated state to an activated state.

Abstract: A method, an apparatus, a system and a computer program product are provided for Bluetooth low energy technology. The method may be carried out by a Bluetooth low energy module. The method may include: detecting an advertisement packet from an advertising device; extracting time information of the advertisement packet; generating a new time information on the basis of the extracted time information; and sending an advertisement packet at the new time information. A system may include a plurality of advertising devices that implement the method, with one of the advertising devices being a master advertiser, and the other advertising devices being slave advertisers.

Abstract: Various techniques for automatic amplitude control of an oscillator are described. An apparatus includes an oscillator circuit configured to generate an oscillating signal. The apparatus includes a feedback circuit configured to control a bias signal of the oscillator circuit to maintain a target peak amplitude of the oscillating signal based on a current-mode indicator of a peak amplitude of the oscillating signal and a reference current. The feedback loop includes a rectifier circuit configured to generate the current-mode indicator and a summing node configured to provide a bias control signal based on a difference between the current-mode indicator and the reference current. The feedback circuit may include a capacitor coupled to the summing node and configured to accumulate charge according to the difference. A magnitude of the current-mode indicator may be at least two orders of magnitude less than a magnitude of the current through an output node of the oscillator circuit.

Abstract: A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.

Abstract: An amplifier topology achieves enhances DC gain to improve linearity while maintaining a good signal to noise ratio. The amplifier includes an amplifier output stage that supplies an amplifier output signal. The amplifier also includes a sense amplifier that augments the output stage. The sense amplifier is coupled to the amplifier input to control current through the output stage in order to achieve reduced voltage variation at the amplifier input as a function of the amplifier output signal voltage as compared to a basic common source amplifier and thereby enhances DC gain of the amplifier.

Abstract: A method includes using a current source to provide a charging current to a capacitor of a resistor-capacitor (RC) tank of an RC oscillator. The method includes using a resistor of the current source as a resistor for the RC tank.

Abstract: An RF receiver includes an RF signal reception path to process an input signal for the receiver for a first mode of the receiver; an oscillator; and a harmonic generator. The harmonic generator generates a harmonic signal in response to operation of the oscillator to replace the input signal with the harmonic signal for a second mode of the receiver.

Abstract: In an exemplary embodiment, an apparatus includes a sensor integrated circuit (IC) that is adapted for ambient light sensing (ALS) and/or proximity detection. The sensor integrated circuit (IC) includes an integrated analog-to-digital converter (ADC) that is adapted to convert at least one signal related to ambient light sensing (ALS) and/or proximity detection to at least one digital signal, and an integrated light emitting diode (LED) driver that is adapted to drive at least one LED. The sensor IC also includes an integrated power management unit (PMU) that is adapted to reduce power dissipation of the sensor IC by running at a low duty cycle the integrated LED driver and the integrated ADC.

Abstract: A system and method whereby a device may operate on two IEEE802.15.4 networks is disclosed. In one embodiment, the multi-network device comprises exactly one radio portion, a processing unit and a computer readable medium, in communication with the processing unit The computer read medium comprises instructions which, when executed, allow the device to share the radio portion among a plurality of IEEE802.15.4 networks. In a further embodiment, the multi-network device acts as a sleepy end device on one of the IEEE802.15.4 networks in which it participates. In another embodiment, it may operate as a coordinator node on one of the plurality of IEEE802.15.4 networks.

Abstract: A transceiver includes a transmit/receive terminal, a receiver input terminal, a plurality of impedance transformation networks coupled in series, a plurality of power amplifiers, and a controller. Each impedance transformation network has first and second ports. The impedance transformation networks include at least one selectable impedance transformation network having a resonant mode and a termination mode. The power amplifiers have outputs respectively coupled to the second ports of corresponding ones of the impedance transformation networks. In a receive mode, the controller selects the resonant mode for each selectable impedance transformation network and disables all power amplifiers. In a transmit mode, the controller enables a selected power amplifier and selects the resonant mode of any upstream selectable impedance transformation network, and selects the termination mode of a downstream selectable impedance transformation network.

Abstract: Disclosed herein are apparatus and methods capable in one example of transmitting a first advertisement packet indicating that an advertising device is scannable; receiving a scan request from at least one scanning device; determining, based on the received one or more scan requests, whether a corresponding one or more scanning device is an allowed for connection; transmitting a second advertisement packet indicating that said advertising device is connectable; and receiving connection requests from the allowed at least one scanning device.

Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.