Abstract: A method includes providing supply voltages to a supply voltage switching circuit that controls routing of the supply voltages to power consuming circuitry associated with the supply voltage switching circuit. The method includes comparing the supply voltages, including using at least one relatively lower precision comparator to compare the supply voltages for a relatively large difference between the supply voltages; and using at least one relatively higher precision comparator to compare the supply voltages for a relatively smaller difference between the supply voltages. The method further includes, based on a result of comparing the supply voltages, selectively coupling the supply voltages to at least one of an isolation well and a power supply rail of the supply voltage switching circuit.

Abstract: A control system for an analog to digital converter (ADC) including a programmable configuration memory, a trigger selector, an input selector, and a conversion controller. The ADC is configurable for adjusting multiple operating parameters including speed and accuracy. The programmable configuration memory stores at least one configuration variable and an input value. The trigger selector enables at least one trigger input. The input selector selects from among multiple analog inputs according to the programmed input value. The conversion controller configures the ADC using the configuration variable, interfaces the input selector to provide an analog input to the ADC, and interfaces the trigger selector to prompt the ADC to perform a conversion process to provide a digital output sample in response to the enabled trigger input.

Abstract: A circuit such as a subscriber line interface circuit (SLIC) has a multiple output power converter including an inductive converter, a first passive rectifier, a first capacitor, and a second passive rectifier. The inductive converter has a voltage input terminal for receiving an input voltage, and a voltage output terminal. The first passive rectifier has an input coupled to the voltage output terminal of the inductive power converter, and an output for providing a first power supply voltage. The first capacitor has a first terminal coupled to the output terminal of the inductive converter, and a second terminal. The second passive rectifier has an input coupled to the second terminal of the first capacitor, and an output terminal for providing a second power supply voltage different from the first power supply voltage.

Abstract: A low energy sensor interface for a microcontroller unit (MCU) is provided. The sensor interface may include a sequencer in operative communication with one or more on-chip peripherals, a count and compare block in communication with one or more sensors and the sequencer, and a highly configurable decoder. The sequencer, the count and compare block and the decoder may be configured to autonomously analyze and collect sensor results using the on-chip peripherals in a low energy mode of operation without intervention from an associated central processing unit (CPU).

Abstract: An apparatus includes a memory, and a control circuit. The memory stores a vector that identifies a signal that is to be provided by an input/output (I/O) interface to a peripheral and indicates a time value. The control circuit is adapted to process the vector and route the identified signal to the peripheral and regulate a time that the signal is routed to the peripheral based on the time value.

Abstract: A system, USB Type-C connector and method are provided herein to transmit encoded data across a USB cable from a transmitter circuit included within a transmitting port of a USB Type-C connector. The method described herein may generally include detecting a voltage generated at a configuration channel (CC) pin of a transmitting port of a USB Type-C connector, setting a voltage at an output node of the transmitter circuit equal to the voltage detected at the CC pin before the output node of the transmitter circuit is connected to the CC pin, subsequently connecting the output node of the transmitter circuit to the CC pin, and transmitting the encoded data from the transmitter circuit through the CC pin to the USB cable.

Abstract: A phase-locked loop uses an edge detect circuit to detect an edge of an input clock signal. The detected edge is used to digitally align an initial edge of the feedback signal with the input clock signal to the PLL so that the feedback signal is substantially aligned with the input clock signal. The edge alignment of the feedback signal may be performed at startup or in response to loss of lock/input clock switching. By aligning the feedback signal the input clock signal based on the edge detect, faster lock occurs.

Abstract: The resolution of a time to digital converter (TDC) is improved by using a gain stage at the input of the fine TDC. A delay line receives a pulse corresponding to the time information and recirculates the pulse in the delay line by coupling an output of the delay line to an input of the delay line. An integrating fine TDC receives a number of pulses from the delay line corresponding to the desired gain.

Abstract: VCONN pull-down circuits and related methods are disclosed for USB Type-C connections. A device is connected through a USB Type-C connection to a separate device using connections including a CC (configuration channel) pin and a VCONN (connection power) pin. The device pulls down the VCONN pin to ground through a resistance (Ra) by applying the voltage on the CC pin to close a switch coupled between the VCONN pin and ground. The device can also be operated in a dead-battery mode where no supply voltage is present for the device. The device can also stop the pull-down on the VCONN pin after a connection is established, for example, using additional switches coupled to a pull-down control signal to remove the CC voltage and open the switch. The voltage on the CC pin can also be clamped to a desired voltage or voltage range using a voltage clamp.

Abstract: Systems and methods are provided that may be implemented to identify and track layer changes of an integrated circuit (IC) device, e.g., during any one of circuit design, pattern generation, device fabrication and/or chip failure analysis processes. Multiple revisions and variants of different IC layers may be identified and tracked using a tracking system and standardized labeling scheme that employs a combination of identifier characters and identifier structures that may be further implemented using revision layer identification parameterized cells (layerID PCells and BooleanID PCells) that include such identifier characters and/or structures The disclosed tracking systems may be further implemented in an automated manner and/or in a manner that allows programming of various parts/aspects and layerID PCells and BooleanID PCells of the tracking system.

Abstract: A technique for reducing jitter in an oscillating signal generated by an oscillator circuit includes reducing feedback of gate leakage current while increasing electrostatic discharge protection and reducing regulated power supply requirements of the oscillator circuit, as compared to conventional oscillator circuits. A circuit includes a first integrated circuit terminal and a thick gate native transistor of a first conductivity type having a first gate terminal having a first gate thickness. The first gate terminal is coupled to the first integrated circuit terminal. The thick gate native transistor has a first threshold voltage. The thick gate native transistor is configured as a source follower. The circuit includes a second transistor of the first conductivity type having a second gate terminal with a second gate thickness less than the first gate thickness. The second gate terminal is coupled to a source terminal of the thick gate native transistor.

Abstract: Circuit configurations and related methods are provided that may be implemented using insulated-gate bipolar transistor (IGBT) device circuitry to protect at risk circuitry (e.g., such as high voltage output buffer circuitry or any other circuitry subject to undesirable ESD events) from damage due to ESD events that may occur during system assembly. The magnitude of the trigger voltage VT1 threshold for an IGBT ESD protection device may be dynamically controlled between at least two different values so that trigger voltage VT1 threshold for an IGBT ESD protection device may be selectively reduced when needed to better enable ESD operation.

Abstract: Embodiments of power detector circuits and related methods to compensate for undesired DC offsets generated within power detector circuits are disclosed. Input signals having input frequencies are received and converted to a magnitude signal, and reference signals are also generated. The magnitude signal may include a DC component proportional to a power of the input signal along with undesired DC offsets. The reference signal may include a DC component proportional to a power of at least one input reference signal along with undesired DC offsets. To compensate for errors introduced by the DC offsets, a DC offset calibration signal or a gain are determined in a calibration mode and then applied in a normal mode to compensate for the DC offsets. For the calibration mode, a difference between the magnitude signal and the reference signal is compared to a threshold value to generate a power detection output signal.

Abstract: A receiver includes first, second, and third signal processors and a controller. The first signal processor provides a first signal in response to detecting a first attribute of a received signal. The second signal processor provides a second signal in response to detecting a second attribute of the received signal. The third signal processor provides a third signal in response to detecting a third attribute of the received signal and provides packet data. The controller enables the first signal processor in response to a receive enable signal, controls the third signal processor to provide the packet data in response to receiving the first signal and the third signal, and initializes the first signal processor and the third signal processor in response to receiving the first signal and the second signal.

Abstract: An apparatus includes a digital battery charger. The digital battery charger includes an analog-to-digital converter (ADC) to convert a terminal voltage of a battery to a first digital signal. The digital battery charger further includes a digital controller coupled to the ADC to receive the first digital signal and provide a set of control signals. The digital battery charger further includes a current digital-to-analog converter (IDAC) coupled to the digital controller to receive the set of control signals and to provide a battery charging current signal.

Abstract: A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.

Abstract: A signal gating circuit includes a logic circuit that receives a stop signal and an input signal and provides an intermediate signal in response, and a pulse stretcher. The pulse stretcher provides an output signal with no pulse when a width of a pulse of the intermediate signal is less than a first amount, with a pulse having a first pulse width that begins after a start of the pulse of the intermediate signal and ends at a predetermined delay thereafter when a pulse width of the intermediate signal is greater than the first amount but less than a second amount, and with a pulse having a second pulse width that begins after the start of the pulse of the intermediate signal and ends after an end of the pulse of the intermediate signal when a pulse width of the intermediate signal is greater than the second amount.

Abstract: A capacitor sense system includes a pad for coupling to an external capacitor. A current digital to analog converter (DAC) supplies current to charge the external capacitor. A reference capacitor is charged by a current source. A first comparator compares a voltage across the external capacitor sensed at the pad to a reference voltage and generates a first comparison. A second comparator compares a voltage across a reference capacitor to the reference voltage and generates a second comparison. The stored first and second comparisons are used to control the current DAC. First and second AC coupling capacitors are coupled respectively between the pad and the first comparator and between the reference capacitor and the second comparator. Sensing at the pad allows more accuracy and the AC coupling capacitors provide better matching and allow for different DC biases to be set for the external capacitor and the first comparator.

Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.

Abstract: In one example, a semiconductor die includes multi-standard, multi-channel expandable television/satellite receiver that can be flexibly implemented in a number of different configurations to enable incorporation into a plurality of different systems. The semiconductor die may include multiple tuners to receive and tune a terrestrial radio frequency (RF) signal and a satellite RF signal. These tuners may include different frequency synthesizers including voltage controlled oscillators (VCOs) to generate VCO signals at different frequencies, mixers to downconvert the RF signals to baseband signals using the VCO signals. In an implementation, the semiconductor die may further include shared circuitry coupled to the tuners to digitize, process and demodulate the baseband signals.