Abstract: A data storage device includes multiple storage modules. Each storage module includes a storage which having a memory device and a first memory controller and a second memory controller. The first memory controller is coupled to the memory device for accessing the memory device. The second memory controller is coupled to the storage for accessing the storage. The first memory controller includes a first transmission interface. The second memory controller includes a second transmission interface. The first memory controller and the second memory controller communicate with each other through the first transmission interface and the second transmission interface.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a system data sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a system data sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region corresponding to the write command is not a system data sub-region, the memory controller writes the data into the first predetermined memory block.

Abstract: A method of managing operation commands for a flash memory includes: providing a first command queue for receiving and storing a plurality of normal operation commands; providing at least one word line read (IWLR) command queue for receiving and storing a plurality of IWLR operation commands; issuing a lock state command between each two consecutive IWLR operation commands to the at least one second command queue; determining a selected command queue from the first command queue and the at least one IWLR command queues according to the lock state command; and delivering an operation command from the selected command queue to the flash memory.

Abstract: The present invention provides a storage device including a controller and methods for operating the storage device and the controller. A controller of a storage device may comprise: an interface controller; a memory controller; a processor configured to transmit downstream commands and upstream commands to the memory controller. The memory controller may be coupled between the interface controller and the processor and may comprise: a first command queue; a second command queue; and a racing handler.

Abstract: The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.

Abstract: A method for performing data access control of a memory device with aid of a predetermined command and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first single command from a host device through a transmission interface circuit of the memory controller; and in response to the first single command conforming to a predetermined format of the predetermined command, utilizing the memory controller to perform a series of operations according to the first single command, wherein the first single command represents a first migrate command, for migrating from a first source logical address to a first destination logical address. The series of operations may include: reading first data at the first source logical address; writing the first data at the first destination logical address; and controlling the memory device to make the first data at the first source logical address become invalid data.

Abstract: A method for use in a flash memory to handle host write commands includes: performing a dummy pattern detection while programing data into a specific section of a first block or a first super block of the flash memory; setting a dummy pattern indicator if all the data that is programmed to the specific section of the first block or the first super block of the flash memory corresponds to a predetermined dummy pattern; and in response to host write commands, modifying a host-to-flash (H2F) address mapping table regarding data that is requested by the host write commands to be programmed to a second block or a second super block of the flash memory without programming the data into the second super block or the second block to complete the host write commands if the dummy pattern indicator is set.

Abstract: A method of handling trim commands in a flash memory is provided. The method comprises: receiving a trim command; modifying logical-to-physical (L2P) address mapping entries of a L2P address mapping table according to the trim command; and storing trim information of the trim command into one of data blocks of the flash memory after modifying the L2P address mapping entries according to the trim command.

Abstract: A method for performing table management of a memory device in a predetermined communications architecture with aid of table error correction and associated apparatus are provided. The method may include: utilizing the memory controller to perform a table error correction procedure to manage at least one table regarding internal management of the memory device, for example: when any error of any table page occurs, searching for a first parity identifier backward, and searching for a second parity identifier forward; selecting a next page of a page storing the first parity identifier to be a first page, selecting a page storing the second parity identifier to be a last page, and preparing at least a set of pages among multiple RAID-protection pages, for being decoded; and performing a RAID decoding operation on the set of pages to generate a recovered table page to be a replacement of the any table page.

Abstract: A method for performing table management of a memory device in predetermined communications architecture with aid of system-region garbage collection (GC) and associated apparatus are provided. The method may include: utilizing the memory controller to perform a system-region GC procedure to manage at least one table regarding internal management of the memory device. The system-region GC procedure may include: reading a set of first table contents from a set of first table pages; and writing the set of first table contents into a set of first system-region-GC-processed table pages of the at least one table block, and writing a first RAID parity of the set of first table contents into a first parity page corresponding to the set of first system-region-GC-processed table pages in the at least one table block, in order to generate a first system-region-GC-processed table RAID protection group, for protecting the set of first system-region-GC-processed table pages.

Abstract: An interface circuit includes a signal processing circuit including multiple signal processing devices and a monitor and calibration module. The monitor and calibration module includes multiple monitor circuits, a processor and a calibration circuit. The monitor circuits monitor at least one of an amplitude, a frequency and a jitter in at least one of a reception signal and a transmission signal to correspondingly generate a monitored result and monitor at least one of power supplying voltage and ground voltage to correspondingly generate a monitored result. The processor collects the monitored results and determines a calibration operation based on the monitored results. The calibration circuit is coupled to the processor and at least one signal processing device and performs the calibration operation on the signal processing device to adjust a characteristic value of the signal processing device.

Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results.

Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device.

Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module. The monitor and calibration module includes multiple monitor circuits, multiple calibration circuits, a compensation accelerator and a processor. The monitor circuits monitor at least one of an amplitude, a frequency and jitter in at least one of a reception signal and a transmission signal to correspondingly generate a monitored result and monitor at least one of power supplying voltage and ground voltage to correspondingly generate a monitored result. The compensation accelerator collects the monitored results and generates a calibration control signal corresponding to each calibration circuit according to calibration commands. The processor generates the calibration commands based on the monitored results.

Abstract: A method for accessing a flash memory module includes: determining a type of data to be written into the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to the type of data, wherein the plurality of sets of encoding/decoding settings correspond to different data lengths, respectively; utilizing the specific encoding/decoding setting to encode the data to generate encoded data; and writing the encoded data into a block of the flash memory module.

Abstract: A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing at least one checking operation to obtain at least one checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device, wherein the L2P table includes address mapping information for accessing the target data, and performing the at least one checking operation to obtain at least one checking result includes checking whether a first L2P-table index pointing toward the L2P table and a second L2P-table index sent from the host device are equivalent to each other; and reading the target data from the NV memory, and sending the target data to the host device.

Abstract: A memory controller includes an error correction code engine, a buffer memory and a microprocessor. In response to a first decoding result of predetermined data, the microprocessor performs a repeated read operation on a memory device to obtain multiple read results of a data chunk having the predetermined data. The data chunk includes multiple bits. The microprocessor further performs a data reconstruction and error correction procedure according to the read results of the data chunk. In an operation of data reconstruction, the microprocessor determines a bit value corresponding to each bit in the data chunk according to the read results of the data chunk to generate a reconstructed data chunk. In an operation of error correction, the microprocessor provides the reconstructed data chunk to the error correction code engine to obtain a second decoding result of the predetermined data.

Abstract: A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table search and associated apparatus are provided. The method may include: utilizing a memory controller to receive a plurality of host commands from a host device through a transmission interface circuit of the memory controller, perform the unbalanced table search to receive a set of first data and a set of second data with first and second active blocks according to first and second commands among the host commands, respectively, and update first and second temporary physical-to-logical (P2L) address mapping tables; and selectively updating a first P2L address mapping table and a second P2L address mapping table according to the first temporary P2L address mapping table and the second temporary P2L address mapping table, respectively, for performing subsequent processing.

Abstract: A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table regions and associated apparatus are provided.

Abstract: A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends an error injection access command signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of the error injection access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, with controlling a memory cell array of flash memory device generating failure errors.