Abstract: A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

Abstract: An interface circuit includes a signal processing circuit configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device. The signal processing circuit includes multiple signal processing devices and a calibration device. The calibration device is coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure.

Abstract: A method and apparatus for performing resuming management are provided. The method includes: utilizing a boot loader to load a group of In-System Programming (ISP) codes; storing information to be retained, including a resume ISP loader, into a retention region of a RAM, for being retained during sleeping; determining whether to start sleeping, and generating a determining result; in response to the determining result, controlling the memory device to start sleeping; after starting sleeping, determining whether a wake-up event occurs; after the wake-up event occurs, executing a first ISP code within the group of ISP codes to start performing a first operation; and executing the resume ISP loader to load other ISP codes within the group of ISP codes.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller configures a first memory block which is a TLC memory blocks as a data buffer, and accordingly configures a plurality of second memory blocks which are SLC memory blocks. The memory controller uses the first memory block to receive data and accordingly store same data in the second memory blocks as backup data. When an amount of available memory space of the first memory block is smaller than or equal to a predetermined amount, the memory controller determines whether any error has occurred in the data stored in the first memory block. When there is any error occurred in the data stored in the first memory block, the memory controller configures a third memory block and move the backup data stored in the second memory block to the third memory block.

Abstract: The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: reading a plurality of physical pages of data in a current block from a flash module during a sudden power off recovery procedure; determining whether a power-supply event has occurred according to an error correction result corresponding to read physical pages; reconstructing a first flash-to-host mapping (F2H) table to include physical-to-logical mapping (P2L) information from the 0th page to a page before a last valid page in the current block when the power-supply event has occurred; and programming the reconstructed first F2H table into a location of the flash module.

Abstract: A memory controller coupled to a memory device and a host device and configured to control access operations of the memory device includes a buffer memory, a host interface, a microprocessor and a data protection engine. The host interface is coupled to the host device and configured to write data received from the host device into the buffer memory and issue a buffer memory write complete notification after the data has been written in the buffer memory. The microprocessor is configured to trigger a data protection operation in response to the buffer memory write complete notification. The protection engine is configured to perform the data protection operation to generate corresponding protection information according to the data written in the buffer memory. The microprocessor is configured to directly trigger the data protection operation after confirming that the data has been written in the buffer memory.

Abstract: A management technology for mapping data of a non-volatile memory is shown. A controller establishes a first mapping table and a second mapping table. By looking up the first mapping table, the controller maps a first logical address issued by the host for data reading to a first block substitute. By looking up the second mapping table, the controller maps the first block substitute to a first physical block of the non-volatile memory. The first mapping table further records a first offset for the first logical address. According to the first offset recorded in the first mapping table, the first logical address is mapped to a first data management unit having the first offset in the first physical block represented by the first block substitute.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for executing an embedded multi-media card (eMMC) command. The method is performed by a processing unit of a flash controller to include: receiving an eMMC command from a host side; and performing a first function associated with a host performance acceleration (HPA) mode according to content of reserved bits of the eMMC command. The HPA mode allows the host side to allocate space in a system memory as an HPA buffer. The HPA buffer stores logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller, and each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device, thereby enabling the host side to issue an HPA read command carrying the physical address to the flash controller.

Abstract: The invention introduces an apparatus for encrypting and decrypting user data, including a memory, a bypass-flag writing circuit and a flash interface controller. The bypass-flag writing circuit writes a bypass flag in a remaining bit of space of the memory that is originally allocated for storing an End-to-End Data Path Protection (E2E DPP), where the bypass flag indicates whether user data has been encrypted. The flash interface controller reads the user data, the E2E DPP and the bypass flag from the memory and programs the user data, the E2E DPP and the bypass flag into the flash device.

Abstract: The invention relates to a method, an apparatus and a computer program product for reading data from multiple flash dies. The method is performed by a processing unit when loading and executing program code to include: issuing a read instruction to a flash interface to drive the flash interface to activate a data read operation for reading data from a location in a die; calculating an output time point corresponding to the read instruction; and issuing a random out instruction corresponding to the read instruction to the flash interface to drive the flash interface to store the data in a random access memory (RAM) when a current time reaches to, or is later than the output time point.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Abstract: A method for performing data access control of a memory device with aid of a predetermined command and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first single command from a host device through a transmission interface circuit of the memory controller; and in response to the first single command conforming to a predetermined format of the predetermined command, utilizing the memory controller to perform a series of operations according to the first single command, wherein the first single command represents a first migrate command, for migrating from a first source logical address to a first destination logical address. The series of operations may include: reading first data at the first source logical address; writing the first data at the first destination logical address; and controlling the memory device to make the first data at the first source logical address become invalid data.

Abstract: A method for performing data access control of a memory device with aid of a predetermined command and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first single command from a host device through a transmission interface circuit of the memory controller; and in response to the first single command conforming to a predetermined format of the predetermined command, utilizing the memory controller to perform a series of operations according to the first single command, wherein the first single command represents a first duplicate command, for duplicating from a first source logical address to a first destination logical address. The series of operations may include: reading first data at the first source logical address; and writing the first data at the first destination logical address.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a predetermined memory block as an active memory block to receive data from a host device and update content of a sub-region bit table in response to a write operation of the active memory block. The sub-region bit table includes one or more bits, each bit is associated with one or more sub-regions and a value of each bit is initially set to a default value. When data of a first logical address received from the host device is written in the active memory block, the memory controller is configured to determine which sub-region the first logical address belongs to and set the value of the bit associated with the sub-region that the first logical address belongs to to a predetermined value different from the default value.

Abstract: A method and apparatus for performing node information exchange management of an all flash array (AFA) server are provided. The method may include: utilizing a hardware manager module among multiple program modules running on any node of multiple nodes of the AFA server to control multiple hardware components in a hardware layer of the any node, for establishing a Board Management Controller (BMC) path between the any node and a remote node among the multiple nodes; utilizing at least two communications paths to exchange respective node information of the any node and the remote node, to control a high availability (HA) architecture of the AFA server according to the respective node information of the any node and the remote node, for continuously providing a service to a user of the AFA server; and in response to malfunction of any communications path, utilizing remaining communications path(s) to exchange the node information.

Abstract: A data storage device includes a memory device including multiple memory blocks corresponding to multiple sub-regions and a memory controller. The memory controller updates content of a read count table in response to a read command with a transfer length greater than 1 for designating more than one logical address to be read. The read count table includes multiple fields recording a read count associated with one sub-region and content of the read count table is updated by increasing the read count(s) associated with the sub-region(s) that logical addresses designated in the read command belong to. The memory controller selects at least one sub-region according to the content of the read count table and performs a data rearrangement procedure to move data of the logical addresses belonging to the selected at least one sub-region to a first memory space of the memory device having continuous physical addresses.

Abstract: A method for performing access management of a memory device in predetermined communications architecture with aid of flexible delay time control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit within the memory controller to dynamically set a delay parameter regarding transmission from the memory device to a host device, for preventing sleeping in delay time(s) corresponding to the delay parameter; utilizing a physical layer (PHY) circuit of the transmission interface circuit to transmit first data from the memory device to the host device, wherein a first delay time starts from a first time point at which transmitting the first data from the memory device to the host device is completed; and utilizing the PHY circuit to start transmitting second data from the memory device to the host device in the first delay time without restarting from sleeping.

Abstract: A multi-screen display control device is shown, which is linked to a host through a universal serial bus (USB) port to receive image data from the host, and uses a plurality of high-definition multimedia interface (HDMI) ports to output a plurality of HDMI sub-images to a plurality of screens. The multi-screen display control device has a USB hub that couples the USB port to a plurality of graphics processing units (GPUs), so that the GPUs generate the HDMI sub-images based on the image data transferred from the host via USB communication technology.

Abstract: An all flash array storage device includes a flash memory array including multiple flash memories and a microprocessor. The flash memories correspond to multiple logical aggregation units. Each logical aggregation unit includes multiple stripes. Each stripe includes multiple storage units, including multiple data units and at least one parity unit. The microprocessor detects a status of the flash memories. In response to a detection result indicating that one of the flash memories has been removed from the flash memory array, the microprocessor sequentially performs a repair operation on the stripes comprised in one or more logical aggregation units that have been written with data. In the repair operation of one stripe, the microprocessor recalculates protection information of the stripe according to content stored in a portion of data units of the stripe and writes the recalculated protection information in one or more storage units of the stripe.