Patents Assigned to Silicon Motion, Inc.
  • Patent number: 12153799
    Abstract: A memory controller for use in a data storage device is provided. The memory controller includes a variable-node circuit and a check-node circuit. The check-node circuit obtains a codeword difference from the variable-node circuit, and calculates a syndrome according to the codeword difference. The variable-node circuit includes a threshold-tracking circuit which is configured to track a threshold used by the variable-node circuit during a low-density parity check (LDPC) decoding process to determine whether the variable-node circuit has entered a trapping status. In response to determining that the variable-node circuit has entered the trapping status during the LDPC decoding process, the variable-node circuit switches a bit-flipping algorithm used by the variable-node circuit during the LDPC decoding process from a first flipping strategy to a post-processing flipping strategy to bring the variable-node circuit out of the trapping status.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: November 26, 2024
    Assignee: SILICON MOTION, INC.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 12153820
    Abstract: A method of performing a wear-leveling operation in a flash memory includes: determining a block age for each of a plurality of blocks in the flash memory according to a number of erase operations that have been performed on the flash memory after the block is erased; selecting one or more candidate source blocks from the plurality of blocks by comparing block ages of the plurality of blocks with an age limit; determining a source block from the one or more candidate source blocks according to erase counts or block ages of the one or more candidate source blocks; and performing the wear-leveling operation on the source block.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: November 26, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Tzu-Yi Yang
  • Publication number: 20240386970
    Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 12149260
    Abstract: A method and apparatus for decoding a Low-Density Parity-Check (LDPC) code whereby the apparatus comprises an LDPC decoder comprising variable-node calculation circuitry and check-node calculation circuitry: the check-node calculation circuitry is arranged operably to perform a modulo 2 multiplication on a codeword and a parity check matrix to calculate a plurality of first syndromes in a first-stage state. The variable-node calculation circuitry is arranged operably to perform a bit flipping algorithm to generate variable nodes, and calculate soft bits for the variable nodes in a second-stage state. The check-node calculation circuitry is arranged to perform the modulo 2 multiplication on the variable nodes and the parity check matrix to calculate second syndromes in the second-stage. When second syndromes indicate that the previously generated variable nodes are incorrect, a third stage state is repeated until decoding succeeds or a total number of iterations exceeds a threshold.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: November 19, 2024
    Assignee: SILICON MOTION, INC.
    Inventors: Shiuan-Hao Kuo, Hung-Jen Huang
  • Patent number: 12147670
    Abstract: A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table regions and associated apparatus are provided.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: November 19, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Chien-Cheng Lin, Chang-Chieh Huang
  • Patent number: 12147334
    Abstract: The invention relates to an apparatus for searching for logical address ranges of host commands. The first comparator outputs logic “0” to the NOR gate when a first end logical address is not smaller than a second start logical address. The second comparator outputs logic “0” to the NOR gate when a second end logical address is not smaller than a first start logical address. The NOR gate outputs logic “1” to a matching register and an output circuitry when receiving logic “0” from both the first and the second comparators. The output circuitry outputs a memory address of a random access memory (RAM) storing a second logical address range from the second start logical address to the second end logical address to a resulting address register when receiving logic “1” from the NOR gate.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: November 19, 2024
    Assignee: SILICON MOTION, INC.
    Inventor: Chun-Yu Chen
  • Publication number: 20240377989
    Abstract: The present invention provides a flash memory controller configured to access a flash memory module. The flash memory controller includes a transmission interface circuit, a buffer memory and a microprocessor. The transmission interface circuit is coupled to a host device, and the transmission interface circuit includes a time queue, at least one virtual queue and a command processing circuit, wherein the command processing circuit is configured to receive a plurality commands from a host device, write information of the plurality of commands into the time queue in sequence, and write the information of at least part of the plurality of commands into the at least one virtual queue. The buffer memory is configured to store the plurality of commands. The microprocessor is configured to selectively read the time queue or the at least one virtual queue to read the information of the plurality of commands.
    Type: Application
    Filed: April 1, 2024
    Publication date: November 14, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Ming-Yu Tsai, Hong-Ren Fang, Hsin-Ying Teng, Shih-Min Yen
  • Publication number: 20240377984
    Abstract: A flash memory controller includes a specific buffer and a processor. The specific buffer allocates a cache space. The processor receives a specific host address sent from the host device, reads and loads a corresponding address pointer mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer linker, determines a specific address pointer corresponding to the specific host address from the corresponding address pointer mapping table according to the specific host address, reads and loads a corresponding address mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer corresponding to the specific host address, and finds a specific flash memory address from the corresponding address mapping table according to the specific host address to perform an access operation in response to the found specific flash memory address.
    Type: Application
    Filed: February 19, 2024
    Publication date: November 14, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Chien-Ting Lin, Wei-Chi Hsu, Chin-Hung Liu
  • Publication number: 20240378146
    Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: dividing a GC operation into a plurality of partial GC operations; determining a default partial GC operation time period for each partial GC operation; determining a partial GC intensity according to at least a basic adjustment factor and an amplification factor; determining the basic adjustment factor according to a type of one or more source blocks corresponding to the GC operation; determining the amplification factor according to a percentage of invalid pages in the one or more source blocks corresponding to the GC operation; and performing the plurality of partial GC operations according to the partial GC intensity and the default partial GC operation time period.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 14, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Chia-Chi Liang, Cheng-Yu Tsai
  • Publication number: 20240377946
    Abstract: A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller includes a second transmission interface. The first transmission interface and the second transmission interface are flash memory interfaces. In a program mode, the first transmission interface receives a first command from the second transmission interface and obtains first transfer data from a bus in response to the first command. A value of the first command is optionally set to a first value or a second value. The first value indicates a memory command transfer operation in a first direction and the second value indicates a memory data transfer operation in the first direction. The first transmission interface processes the first transfer data according to the value of the first command to obtain a memory command or written data.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 14, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Chen-Hao Chen, Shih-Hsiang Shen, Hui-Lin Liu
  • Publication number: 20240378162
    Abstract: A bridge device for bridging a host device and a data storage device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller is coupled to the first controller and includes a second transmission interface. The second transmission interface is coupled to the first transmission interface through a bus. The first transmission interface operates in a slave mode and the second transmission interface operates in a master mode. The first transmission interface and the second transmission interface generate multiple transfer data chunks in compliance with a common bridge transfer format to perform transfer operations in dual directions for respectively transferring a command and data between a host device and a data storage device.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 14, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Chen-Hao Chen, Shih-Hsiang Shen, Hui-Lin Liu
  • Patent number: 12141460
    Abstract: A method for performing data access management of an all flash array (AFA) server and the AFA server operating according to the method are provided. The method includes: utilizing an upper layer program module running on a first node to detect whether any request from a client device of a user is received; in response to a write request, utilizing an intermediate layer program module to mirror data corresponding to the write request to a second node; and before the intermediate layer program module flushing the data to a lower layer program module, in response to the data being mirrored from a first volatile memory of the first node to a second volatile memory of the second node, utilizing the intermediate layer program module to send an acknowledgement to the client device without checking whether the data has been protected in any non-volatile memory of any of the multiple nodes.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: November 12, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Yi-Feng Lin
  • Patent number: 12141475
    Abstract: A method of a storage device to be externally coupled to a host device via a specific communication interface includes: providing a flash memory unit comprising at least one flash memory; counting an outstanding command number for at least one submission queue which is used for storing information of unfinished commands; counting a completion command number for at least one completion queue which is used for storing information of finished commands; and, generating and outputting an interrupt event from the storage device to the host device when a comparison result of the counted outstanding command number with the counted completion command number matches a specific condition.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: November 12, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Tzu-Yi Yang
  • Patent number: 12141060
    Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: dividing a GC operation into a plurality of partial GC operations; determining a default partial GC operation time period for each partial GC operation; determining a partial GC intensity according to at least a basic adjustment factor and an amplification factor; determining the basic adjustment factor according to a type of one or more source blocks corresponding to the GC operation; determining the amplification factor according to a percentage of invalid pages in the one or more source blocks corresponding to the GC operation; and performing the plurality of partial GC operations according to the partial GC intensity and the default partial GC operation time period.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: November 12, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Chia-Chi Liang, Cheng-Yu Tsai
  • Publication number: 20240370367
    Abstract: A method for performing garbage collection (GC) management of a memory device with aid of block classification and associated apparatus are provided. The method may include: utilizing a memory controller to divide at least one portion of blocks among a plurality of blocks into multiple first blocks belonging to at least one first type in a first area and multiple second blocks belonging to at least one second type in a second area; utilizing the memory controller to receive a first command from a host device through a transmission interface circuit within the memory controller; and during writing data in response to the first command, performing a foreground GC procedure to control the memory device to perform GC before completing at least one writing operation corresponding to the first command, for controlling priority of releasing storage space of the second area to be higher than that of the first area.
    Type: Application
    Filed: May 2, 2024
    Publication date: November 7, 2024
    Applicant: Silicon Motion, Inc.
    Inventor: Cheng-Yu Tsai
  • Patent number: 12135889
    Abstract: The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: November 5, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Ching-Hui Lin
  • Publication number: 20240361919
    Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module. A process monitor monitors a current or a voltage of a test element to generate a process detection result. A temperature monitor monitors an environment temperature to generate a temperature monitored result. A calibration circuit performs calibration operation on a signal processing device according to a preferred reference value subset to adjust a characteristic value of the signal processing device. A compensation control mechanism operation logic selects the preferred reference value subset from multiple reference value subsets according to the process detection result and the temperature monitored result and generates a calibration control signal to control the calibration operation of the calibration circuit.
    Type: Application
    Filed: July 24, 2023
    Publication date: October 31, 2024
    Applicant: Silicon Motion, Inc.
    Inventor: Fu-Jen Shih
  • Publication number: 20240361934
    Abstract: A data storage device includes a memory device and a memory controller. In response to a write command received from a host device, the memory controller performs a write operation to write predetermined data into the memory device. In the write operation, the memory controller selects one from multiple superblocks as a first target superblock of the write operation and sequentially writes the portions of the predetermined data into the pages of the first target superblock in a cyclic manner among memory dies according to an order of plane indices. Each memory die includes at least a first plane and a second plane. In the write operation corresponding to the predetermined data, corresponding write operations performed on a first page on the first plane of all memory dies are earlier than corresponding write operations performed on a first page on the second plane of all memory dies.
    Type: Application
    Filed: July 25, 2023
    Publication date: October 31, 2024
    Applicant: Silicon Motion, Inc.
    Inventor: Chi-Hung Cheng
  • Publication number: 20240363183
    Abstract: A method for calibrating a characteristic value of a signal processing device comprised in SerDes inside of an interface circuit of a memory controller includes: monitoring a current of a voltage of a test element to generate a process detection result by a monitor and calibration module; monitoring an environment temperature to generate a temperature monitored result by the monitor and calibration module; selecting a reference value subset from multiple reference value subsets as a preferred reference value subset for a calibration operation based on the process detection result and the temperature monitored result; and performing the calibration operation on the signal processing device by at least one calibration circuit of the monitor and calibration module according to the preferred reference value subset to adjust the characteristic value of the signal processing device.
    Type: Application
    Filed: July 24, 2023
    Publication date: October 31, 2024
    Applicant: Silicon Motion, Inc.
    Inventor: Fu-Jen Shih
  • Patent number: 12131035
    Abstract: A method for performing data access management of a memory device in predetermined communications architecture to enhance sudden power off recovery (SPOR) of page-group-based redundant array of independent disks (RAID) protection with aid of multi-table control using dummy flag and associated apparatus are provided. The method may include: after occurrence of a sudden power off (SPO) event, utilizing the memory controller to perform a SPOR procedure in response to the SPO event, for example, updating a temporary physical-to-logical (P2L) address mapping table corresponding to a first active block to carry the dummy flag in each P2L table entry of at least one P2L table entry corresponding to at least one set of damaged pages; and after performing the SPOR procedure in response to the SPO event, utilizing the memory controller to write subsequent data into at least one set of subsequent pages in the damaged page group.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: October 29, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Ting-Fong Hsu, Szu-I Yeh