Patents Assigned to Siltronic AG
  • Patent number: 7868325
    Abstract: Semiconductor wafer of monocrystalline silicon contain fluorine, the fluorine concentration being 1·1010 to 1·1016 atoms/cm3, and is free of agglomerated intrinsic point defects whose diameter is greater than or equal to a critical diameter. The semiconductor wafers are produced by providing a melt of silicon which is doped with fluorine, and crystallizing the melt to form a single crystal which contains fluorine within the range of 1·1010 to 1·1016 atoms/cm3, at a growth rate at which agglomerated intrinsic point defects having a critical diameter or larger would arise if fluorine were not present or present in too small an amount, and separating semiconductor wafers from the single crystal.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: January 11, 2011
    Assignee: Siltronic AG
    Inventor: Wilfried von Ammon
  • Publication number: 20100330885
    Abstract: A method for polishing the edge of a semiconductor wafer comprises (a) providing a semiconductor wafer which has been polished on its side surfaces and which has a rounded edge; (b) polishing the edge of the wafer by fixing the semiconductor wafer on a centrally rotating chuck, delivering the wafer to a centrally rotating polishing drum, which is inclined with respect to the chuck and to which a polishing pad containing fixedly bonded abrasives is applied, and pressing semiconductor wafer and polishing drum onto one another while a polishing agent solution containing no solids is continuously supplied.
    Type: Application
    Filed: May 5, 2010
    Publication date: December 30, 2010
    Applicant: SILTRONIC AG
    Inventor: Juergen Schwandner
  • Publication number: 20100330882
    Abstract: A semiconductor wafer is polished, wherein in a first step, the rear side of the wafer is polished by a polishing pad comprising fixedly bonded abrasives having a grain size of 0.1-1.0 ?m, while supplying a polishing agent free of solid materials having a pH of at least 11.8, and, in a second step, the front side of the semiconductor wafer is polished, wherein a polishing agent having a pH of less than 11.8 is supplied. A polishing pad for use in apparatuses for polishing semiconductor wafers, has a layer containing abrasives, a layer composed of a stiff plastic and also a compliant, non-woven layer, wherein the layers are bonded to one another by means of pressure-sensitive adhesive layers.
    Type: Application
    Filed: May 5, 2010
    Publication date: December 30, 2010
    Applicant: SILTRONIC AG
    Inventors: Juergen Schwandner, Roland Koppert
  • Publication number: 20100330883
    Abstract: The edge region of one side of a semiconductor wafer is polished by pressing the wafer by means of a rotatable polishing head against a polishing pad lying on a rotating polishing plate, and containing fixed abrasive. The polishing head is provided with a resilient membrane radially subdivided into a plurality of chambers by gas or liquid cushions, the polishing pressure independently selectable for each chamber. The wafer is held in position during polishing by a retainer ring pressed against the polishing pad with an application pressure, a polishing agent is introduced between the wafer and the polishing pad, and the polishing pressure exerted on the wafer in a chamber lying in the edge region of the wafer of the polishing head, and the application pressure of the retainer ring, are selected so that material is essentially removed only at the edge of the wafer.
    Type: Application
    Filed: May 5, 2010
    Publication date: December 30, 2010
    Applicant: Siltronic AG
    Inventor: Juergen Schwandner
  • Publication number: 20100330881
    Abstract: Semiconductor wafers are double sided polished by a method of polishing a frontside of the wafer in a first step with a polishing pad with fixed abrasive and simultaneously polishing a backside of the wafer with a polishing pad containing no abrasive, but during which an abrasive polishing agent is introduced between the polishing pad and the backside of the wafer, inverting the wafer, and then in a second step polishing the backside of the wafer with a polishing pad containing fixed abrasive and simultaneously polishing the frontside of the wafer with a polishing pad containing no fixed abrasive, a polishing agent containing abrasive being introduced between the polishing pad and the frontside of the semiconductor wafer.
    Type: Application
    Filed: April 30, 2010
    Publication date: December 30, 2010
    Applicant: SILTRONIC AG
    Inventor: Juergen Schwandner
  • Publication number: 20100327414
    Abstract: Semiconductor wafers are produced by a process of: a) providing a semiconductor wafer by cutting a silicon ingot into wafers; b) rounding the edge of the wafer, so that the wafer comprises plane surfaces on the frontside and backside and rounded oblique surfaces in the edge region; c) polishing the frontside and backside of the wafer, the frontside being polished by chemical-mechanical polishing using a polishing pad which is free of abrasive fixed in the polishing pad; backside polishing being carried out in three steps, using a polishing pad containing fixed abrasive which is pressed onto the backside of the wafer, a polishing agent free of solids introduced between the polishing pad and the backside of the wafer in the first step, a polishing agent containing abrasive being introduced in the second and third steps, a polishing pressure of 8-15 psi in the first and second steps being reduced to 0.5-5 psi in the third step.
    Type: Application
    Filed: May 12, 2010
    Publication date: December 30, 2010
    Applicant: SILTRONIC AG
    Inventor: Juergen Schwandner
  • Publication number: 20100330786
    Abstract: Epitaxially coated semiconductor wafers are produced by minimally the following steps in the order specified: (a) depositing an epitaxial layer on one side of a semiconductor wafer; (b) first polishing the epitaxially coated side of the semiconductor wafer with a polishing pad with fixed abrasive while supplying a polishing solution which is free of solids; (c) CMP polishing of the epitaxially coated side of the semiconductor wafer with a soft polishing pad which contains no fixed abrasive, while supplying a polishing agent suspension; (d) depositing another epitaxial layer on the previously epitaxially coated and polished side of the semiconductor wafer.
    Type: Application
    Filed: June 10, 2010
    Publication date: December 30, 2010
    Applicant: SILTRONIC AG
    Inventors: Juergen Schwandner, Roland Koppert
  • Publication number: 20100323585
    Abstract: A semiconductor wafer processed on both sides simultaneously, the wafer lying in freely movable fashion in a cutout in one of a plurality of carriers that rotate by means of a rolling apparatus, and one thereby being moved on a cycloidal trajectory, the semiconductor wafer being processed in material-removing fashion between two rotating ring-shaped working disks, wherein each working disk comprises a working layer comprising abrasive material, and wherein an alkaline medium comprising no abrasive material is supplied during the processing.
    Type: Application
    Filed: April 6, 2010
    Publication date: December 23, 2010
    Applicant: Siltronic AG
    Inventor: Juergen Schwandner
  • Publication number: 20100316551
    Abstract: The invention relates to a method for pulling a silicon single crystal from a melt which is contained in a crucible, comprising immersion of a seed crystal into the melt; crystallization of the single crystal on the seed crystal by raising the seed crystal from the melt with a crystal pull speed; widening the diameter of the single crystal to a setpoint diameter in a conical section, comprising control of the crystal pull speed in such a way as to induce a curvature inversion of a growth front of the single crystal in the conical section.
    Type: Application
    Filed: March 16, 2010
    Publication date: December 16, 2010
    Applicant: SILTRONIC AG
    Inventor: Markus Baer
  • Publication number: 20100294197
    Abstract: Epitaxially coated silicon wafers are produced by placing a wafer polished on its front side on a susceptor in an epitaxy reactor, first pretreating under a hydrogen atmosphere and in a second and a third step with addition of an etching medium to the hydrogen atmosphere, and subsequently providing an epitaxial layer, wherein during the first and second steps the hydrogen flow rate is 20-100 slm, during the second and third steps the flow rate of the etching medium is 0.5-1.5 slm, during the second step the average temperature in the reactor chamber is 950-1050° C., and the power of heating elements above and below the susceptor is regulated such that there is a temperature difference of 5-30° C. between a radially symmetrical region encompassing the central axis of and a part lying outside this region; and during the third step the hydrogen flow rate is reduced to 0.5-10 slm. In a second method, during the third pretreatment step the flow rate of the etching medium is increased to 1.
    Type: Application
    Filed: April 23, 2010
    Publication date: November 25, 2010
    Applicant: Siltronic AG
    Inventor: Joerg Haberecht
  • Patent number: 7838398
    Abstract: In a method for producing epitaxially coated semiconductor wafers, a multiplicity of prepared, front side-polished semiconductor wafers are successively coated individually with an epitaxial layer on their polished front sides at temperatures of 800-1200° C. in a reactor, while supporting the prepared semiconductor wafer over a susceptor having a gas-permeable structure, on a ring placed on the susceptor which acts as a thermal buffer between the susceptor and the supported semiconductor wafer, the semiconductor wafer resting on the ring, and its backside facing but not contacting the susceptor, so that gaseous substances are delivered from a region over the backside of the semiconductor wafer by gas diffusion through the susceptor into a region over the backside of the susceptor, the semiconductor wafer contacting the ring only in an edge region of its backside, wherein no stresses measurable by means of photoelastic stress measurement (“SIRD”) occur in the semiconductor wafer.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: November 23, 2010
    Assignee: Siltronic AG
    Inventors: Reinhard Schauer, Norbert Werner
  • Publication number: 20100291756
    Abstract: Semiconductor structures are produced by providing a 3C—SiC semiconductor layer containing a monocrystalline 3C—SiC layer by implantation of carbon in silicon on a first silicon substrate and applying an epitaxial layer of nitride compound semiconductor suitable for the generation of optoelectronic components onto the 3C—SiC semiconductor layer structure, wherein the epitaxial layer of nitride semiconductor is transferred onto a second substrate by bonding the nitride layer onto the second substrate surface and mechanically or chemically removing silicon and layers containing SiC, the second substrate being a metal with a reflectivity ?80% or being substantially transparent.
    Type: Application
    Filed: January 21, 2009
    Publication date: November 18, 2010
    Applicant: SILTRONIC AG
    Inventors: Maik Haeberlen, Brian Murphy
  • Publication number: 20100291761
    Abstract: A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order: simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.
    Type: Application
    Filed: March 16, 2010
    Publication date: November 18, 2010
    Applicant: SILTRONIC AG
    Inventors: Peter Storck, Thomas Buschhardt
  • Publication number: 20100288185
    Abstract: Silicon single crystals are grown from the melt by providing the melt in a crucible; imposing a horizontal magnetic field on the melt; directing a gas between the single crystal and a heat shield to a melt free surface, and controlling the gas to flow over a region of the melt free surface extending in a direction substantially perpendicular to the magnetic induction. A suitable apparatus has a crucible for holding the melt; a heat shield surrounding the silicon single crystal having a lower end which is connected to a bottom cover facing a melt free surface and a non-axisymmetric shape with respect to a crucible axis, such that gas which is directed between the crystal and the heat shield to the melt free surface is forced to flow over a region of the melt which extends substantially perpendicular to the magnetic induction.
    Type: Application
    Filed: April 23, 2010
    Publication date: November 18, 2010
    Applicant: SILTRONIC AG
    Inventor: Piotr Filar
  • Patent number: 7828893
    Abstract: A silicon wafer having no epitaxially deposited layer or layer produced by joining to the silicon wafer, with a nitrogen concentration of 1·1013-8·1014 atoms/cm3, an oxygen concentration of 5.2·1017-7.5·1017 atoms/cm3, a central thickness BMD density of 3·108-2·1010 cm?3, a cumulative length of linear slippages ?3 cm and a cumulative area of areal slippage regions ?7 cm2, the front surface having <45 nitrogen-induced defects of >0.13 ?m LSE in the DNN channel, a layer at least 5 ?m thick, in which ?1·104 COPs/cm3 with a size of ?0.09 ?m occur, and a BMD-free layer ?5 ?m thick. Such wafers may be produced by heat treating the silicon wafer, resting on a substrate holder, a specific substrate holder used depending on the wafer doping. For each holder, maximum heating rates are selected to avoid formation of slippages.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: November 9, 2010
    Assignee: Siltronic AG
    Inventors: Timo Mueller, Wilfried von Ammon, Erich Daub, Peter Krottenthaler, Klaus Messmann, Friedrich Passek, Reinhold Wahlich, Arnold Kuehhorn, Johannes Studener
  • Patent number: 7829467
    Abstract: Semiconductor wafers are cut from a crystal and subjected to a series of processing steps in which material is removed from a front side and a rear side of the semiconductor wafers, comprising the following processing steps: a mechanical processing step, an etching step in which the semiconductor wafers are oxidized and material is removed from the front side of the wafers with the aid of a gaseous etchant containing hydrofluoric acid at a temperature of 20 to 70° C., and a polishing step in which the front side of the semiconductor wafer is polished, the processing steps in which the front side of the semiconductor wafer is polished causing material removal which does not amount to more than 5 ?m in total.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: November 9, 2010
    Assignee: Siltronic AG
    Inventors: Maximilian Stadler, Günter Schwab, Diego Feijóo, Karlheinz Langsdorf
  • Patent number: 7828897
    Abstract: A pulling apparatus and a method with which especially heavy crystals (5) can be pulled using the Czochralski method utilizing the pulling apparatus. For this purpose the neck (4) of the crystal (5) has an enlargement (10) beneath which extends the support device. This device includes latches (7), which are moved from a resting position into an operating position in which the latches (7) extend beneath the enlargement (10). Each latch (7) is supported on the base body such that it is swivellable about a pivot axis (8) and can assume two stable positions, namely the resting position and the operating position. Each of these positions is defined by a stop on the base body. When the latch rests on the one stop, its center of gravity, viewed from the neck (4), is located on the other side of the pivot axis (8). When the latch rests on the other stop, the center of gravity is located on this side of the pivot axis (8).
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: November 9, 2010
    Assignees: Crystal Growing Systems GmbH, Siltronic AG
    Inventors: Burkhard Altekrüger, Stefan Henkel, Axel Vonhoff, Erich Tomzig, Dieter Knerer
  • Patent number: 7827980
    Abstract: A multiplicity of wafers are sliced from a workpiece which has a longitudinal axis and a cross section, the workpiece fastened on a table being fed by a relative movement directed perpendicularly to the longitudinal axis of the workpiece between the table and the wire gang of a wire saw, with a variable forward feed rate through the wire gang formed by a sawing wire moved with an effective speed, the effective speed of the sawing wire being regulated as a function of the forward feed rate and the workpiece cross section so as to result in uniform wear of the sawing wire.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: November 9, 2010
    Assignee: Siltronic AG
    Inventors: Frank Skovgaard-Soerensen, Matthias Mahnke, Thomas Kasinger
  • Patent number: 7820549
    Abstract: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 ?m, a DeltaWarp of less than 30 ?m, a bow of less than 10 ?m and a DeltaBow of less than 10 ?m. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: October 26, 2010
    Assignee: Siltronic AG
    Inventors: Markus Blietz, Robert Hoelzl, Reinhold Wahlich, Andreas Huber
  • Patent number: 7815736
    Abstract: An apparatus for supporting a single crystal during Czochralski crystal pulling below a thickened crystal neck has lower bearing surface(s) with a central opening inscribable with a horizontal circle of diameter D1, centered on a vertical axis, the bearing surface(s) connected by connecting element(s) to minimally one securing element for securing to a crystal pulling lifting device, the connecting elements arranged to provide a clear-space in the region above the bearing surface(s) in which a circle of diameter D2 centered on the vertical axis (D2>D1) is inscribable over a length of the vertical axis. The unitary apparatus is useful for crystal ingot growth by immersion into the semiconductor melt prior to growth of a Dash neck and a thickening of the Dash neck. The apparatus is then raised to support the crystal by bearing against the bottom of the thickening.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: October 19, 2010
    Assignee: Siltronic AG
    Inventor: Dieter Knerer