Abstract: The invention relates to a process for manufacturing a multilayered semiconductor wafer comprising a handle wafer (5) and a layer (40) comprising silicon carbide bonded to the handle wafer (5), the process comprising the steps of: a) providing a handle wafer (5), b) providing a donor wafer (1) comprising a donor layer (2) and a remainder (3) of the donor wafer, the donor layer (2) comprising monocrystalline silicon, e) bonding the donor layer (2) of the donor wafer (1) to the handle wafer (5), and f) removing the remainder (3) of the donor wafer in order to expose the donor layer (2) which remains bonded to the handle wafer (5), the process being characterized by further steps of c) implanting carbon ions into the donor layer (2) in order to produce a layer (4) comprising implanted carbon, and d) heat-treating the donor layer (2) comprising the layer (4) comprising implanted carbon in order to form a silicon carbide donor layer (44) in at least part of the donor layer (2).

Abstract: A method for detection of mechanical defects in a semiconductor ingot section which has at least one planar surface, and a thickness at right angles to this surface of 1 cm to 100 cm, involves scanning the planar surface by at least one ultrasound head which is coupled via a liquid coupling medium to the planar surface and, at each measurement point (x,y) producing at least one ultrasound pulse which is directed at the planar surface of the ingot section, recording the ultrasound-pulse echo as a function of time, such that an echo from the planar surface, an echo from a surface opposite the planar surface, and further echoes are detected, with the positions (xp, yp, zp) of mechanical defects in the ingot section being determined from the further echoes.

Abstract: A method of polishing a semiconductor wafer includes applying a polishing pad to the semiconductor wafer so as to subject the semiconductor wafer to a polishing process and supplying an aqueous polishing agent solution between the polishing pad and the semiconductor wafer. The polishing pad includes fixedly bonded abrasives of SiO2 with an average grain size in a range of 0.1 to 1.0 ?m. The aqueous polishing agent solution comprising an alkaline component, being free of solid materials and having a variable pH value in a range of 11 to 13.5. The aqueous polishing agent solution is maintained at a pH value of less than 13 during the polishing process and the pH value of the aqueous polishing agent solution is increased to a range of 13 to 13.5 so as to end the polishing process.

Abstract: A method for double-side polishing of a semiconductor wafer includes situating the semiconductor wafer in a cutout of a carrier that is disposed in a working gap between an upper polishing plate covered by a first polishing pad and a lower polishing plate covered by a second polishing pad. The first and second polishing pads each include tiled square segments that are formed by an arrangement of channels on the pads, where the square segments of the first pad are larger than the segments of the second pad. The square segments of the polishing pads include abrasives. During polishing, the carrier is guided such that a portion of the wafer temporarily projects laterally outside of the working gap. A polishing agent with a pH that is variable is supplied during polishing at a pH in a range of 11 to 12.5 during a first step and at a pH of at least 13 during a second step.

Abstract: A method of polishing a semiconductor wafer includes polishing a surface of the semiconductor wafer using a polishing pad while supplying a polishing agent slurry containing abrasives during a first step. The polishing pad is free of abrasives and includes a first surface that contacts the semiconductor wafer, the first surface having a surface structure including elevations. Supply of polishing agent slurry is subsequently ended and, in a second step, the surface of the semiconductor wafer is polished using the polishing pad while supplying a polishing agent solution having a pH value of at least 12 that is free of solids.

Abstract: A two layer LTO backside seal for a wafer. The two layer LTO backside seal includes a low stress LTO layer having a first major side and a second major side, the first major5 side of the low stress LTO layer adjacent to one major side of the wafer. The two layer LTO backside seal further includes a high stress LTO layer having a first major side and second major side, the first major side of the high stress LTO layer adjacent the second major side of the low stress LTO layer.

Abstract: Silicon single crystals are pulled from a melt in a crucible, the single crystal surrounded by a heat shield, the lower end of which is a distance h from the melt surface, wherein gas flows downward between the single crystal and the heat shield, outward between the lower end of the heat shield and the melt, and then upward in the region outside the heat shield. The internal diameter of the heat shield at its lower end is 55 mm or more than the diameter of the single crystal, and the radial width of the heat shield at its lower end is not more than 20% of the diameter of the single crystal. Highly doped single crystals pulled accordingly have a void concentration ?50 m?3.

Abstract: A method for slicing a plurality of wafers from a crystal includes providing a crystal of semiconductor material having a longitudinal axis, a cross section and at least one pulling edge. The crystal is fixed on a table and guided through a wire gang defined by sawing wire so as to form the wafers. The guiding is provided by a relative movement between the table and the wire gang such that entry sawing or exit sawing using the sawing wire occurs in a vicinity of the at least one pulling edge of the crystal.

Abstract: Dislocation-free single-crystal silicon is manufactured by the Czochralski method, wherein silicon which does not contain particles with an average particle diameter smaller than 250 ?m, is used as raw material for melting.

Abstract: Semiconductor wafers composed of silicon with an epitaxially deposited layer, are prepared by: placing a dummy wafer on a susceptor of an epitaxy reactor; conducting an etching gas through the epitaxy reactor in order to remove residues on surfaces in the epitaxy reactor through the action of the etching gas; conducting a first deposition gas through the epitaxy reactor in order to deposit silicon on surfaces in the epitaxy reactor; replacing the dummy wafer by a substrate wafer composed of silicon; and conducting a second deposition gas through the epitaxy reactor in order to deposit an epitaxial layer on the substrate wafer.

Abstract: Silicon single crystals are prepared from molten granules, by producing a first volume of molten silicon between a growing single crystal and the lower end of a silicon conical tube which is closed at its lower end, and encloses a central opening of a rotating silicon plate below which the tube extends, by means of a first induction heating coil arranged below the plate; producing a second volume of molten silicon by a second induction heating coil arranged above the plate; melting the lower end of the tube to form a passage for the second volume of molten silicon, the passage produced at a point in time when the second volume is not yet present or is less than double the volume of the first volume; and crystallizing monocrystalline silicon on the growing single crystal with consumption of molten silicon from the first and the second volume.

Abstract: To reduce and homogenize the thickness of a semiconductor layer which lies on the surface of an electrically insulating material, the surface of the semiconductor layer is exposed to the action of an etchant whose redox potential is adjusted as a function of the material and the desired final thickness of the semiconductor layer, so that the material erosion per unit time on the surface of the semiconductor layer due to the etchant becomes less as the thickness of the semiconductor layer decreases, and is only from 0 to 10% of the thickness per second when the desired thickness is reached. The method is carried out without the action of light or the application of an external electrical voltage.

Abstract: A method of producing a semiconductor wafer includes a plurality of steps carried out in the following order. Simultaneous double-side material-removal processing is carried out on a semiconductor wafer sliced from a single crystal by processing the semiconductor wafer between two rotating ring-shaped working disks. Each working disk includes first abrasives having an average grain size in a range of 5.0 to 20.0 ?m. Both sides of the semiconductor wafer are treated with an alkaline medium. Grinding of the front and rear sides of the semiconductor wafer is carried out. For the grinding of each side a first side is held using a wafer holder and the other side is processed using a grinding tool. The grinding tool includes second abrasives having an average grain size that is smaller than the average grain size of the first abrasives and having an average grain size being in a range of 1.0 to 10.0 ?m.

Abstract: Silicon semiconductor wafers are produced by: pulling a single crystal with a conical section and an adjoining cylindrical section having a diameter ?450 mm and a length of ?800 mm from a melt in a crucible, wherein in pulling the transition from the conical section to the cylindrical section, the pulling rate is at least 1.8 times higher than the average pulling rate during the pulling of the cylindrical section; cooling the growing single crystal with a cooling power of at least 20 kW; feeding heat from the side wall of the crucible to the single crystal, wherein a gap having a height of ?70 mm is present between a heat shield surrounding the single crystal and the melt surface.

Abstract: A polished semiconductor wafer has a front surface and a back surface and an edge R, which is located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer. The maximum deviation of the flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface is 0.7 ?m or less. A process for producing the semiconductor wafer, comprises at least one treatment of the semiconductor wafer with a liquid etchant and at least one polishing of at least a front surface of the semiconductor wafer, the etchant flowing onto a boundary of the semiconductor wafer during the treatment, and the boundary of the semiconductor wafer which faces the flow of etchant being at least partially shielded from being struck directly by the etchant. The shielding extends in the direction of a thickness d of the semiconductor wafer and is at least d+100 ?m long.

Abstract: A sawing strip for fixing a substantially cylindrical workpiece when cutting off slices from this workpiece with a wire saw has a first face, which is concavely curved perpendicular to its longitudinal direction for connecting to the workpiece, a second face opposite the first face for connecting to a mounting plate, and two side faces which connect the first face and the second face, two edges of the sawing strip at which the side faces meet the first face at a distance a from each other, an imaginary line on the first face marking its minimum distance d from the second face, the side faces being at a distance b, measured at the height of the line and perpendicular to the distance d, wherein the distance b is less than the distance a. The sawing strip is useful for decreasing waviness of wafers cut from a cylindrical workpiece using the sawing strip.

Abstract: A silicon wafer includes BMDs with a diagonal length of from 10 nm to 50 nm, and has a density of BMD which exists at a depth of 50 ?m and deeper from the surface of the silicon wafer which is greater than or equal to 1×1011/cm3, and a ratio of the {111} plane of the BMD to the total planes surrounding the BMD, as an indication of the morphology of the BMD, is less than or equal to 0.3.

Abstract: Silicon wafers, are manufactured with which a desired strength and electric resistance of a semiconductor device can be obtained. A non-oxidizing heat treatment for oxygen out-diffusion is performed wherein the desired amount of oxygen is discharged from the surface layer of the silicon substrate. By this heat treatment for oxygen out-diffusion, a surface layer having a low oxygen content is formed on the silicon substrate, the heat treatment of the silicon substrate being performed through an oxide film.

Abstract: Silicon wafers doped with nitrogen, hydrogen and carbon, have a plurality of voids, wherein 50% or more of the total number of voids are bubble-like shaped aggregates of voids; a V1 region having a void density of over 2×104/cm3 and below 1×105/cm3 which occupies 20% or less of the total area of the silicon wafer; a V2 region having a void density of 5×102 to 2×104/cm3 which occupies 80% or more of the total area of said silicon wafer; and a bulk micro defect density which is 5×108/cm3 or more, have excellent GOI characteristics and a high C-mode pass rate. The wafers are cut from a single crystal pulled by a method in which carbon, nitrogen, and hydrogen dopants are controlled, and the crystal is subjected to rapid cooling.

Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.