Patents Assigned to Siltronic AG
  • Patent number: 8268708
    Abstract: Silicon wafers polished on their front sides are individually placed on a susceptor in an epitaxy reactor and firstly pretreated under a hydrogen atmosphere, and secondly with addition of an etching medium with a flow rate of 1.5-5 slm to the hydrogen atmosphere, the hydrogen flow rate being 1-100 slm in both steps, and subsequently epitaxially coated on the polished front side, and then removed from the reactor. In a second method, gas flows introduced into the reactor by injectors are distributed into outer and inner zones of the chamber, such that the inner zone gas flow acts on a wafer central region and the outer zone gas flow acts on a wafer edge region, the inner/outer distribution of the etching medium I/O=0-0.75. Silicon wafers having an epitaxial layer having global flatness value GBIR of 0.02-0.06 ?m, relative to an edge exclusion of 2 mm are produced.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: September 18, 2012
    Assignee: Siltronic AG
    Inventors: Joerg Haberecht, Christian Hager, Georg Brenninger
  • Patent number: 8242020
    Abstract: A method for producing a semiconductor wafer. The method includes placing the semiconductor wafer in a cutout in a carrier. Both sides of the semiconductor wafer are polished between an upper and a lower polishing plate with a polishing agent until the thickness of the center of the semiconductor wafer is less than the thickness of the carrier and from 10 ?m to 30 ?m of semiconductor wafer material is removed. The polishing agent contains 0.1 to 0.4% by weight of SiO2 and 0.1 to 0.9% by weight of an alkaline component.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: August 14, 2012
    Assignee: Siltronic AG
    Inventors: Klaus Roettger, Gerhard Heier, Alexander Heilmaier
  • Patent number: 8241421
    Abstract: The epitaxial layer defects generated from voids of a silicon substrate wafer containing added hydrogen are suppressed by a method for producing an epitaxial wafer by: growing a silicon crystal by the Czochralski method comprising adding hydrogen and nitrogen to a silicon melt and growing from the silicon melt a silicon crystal having a nitrogen concentration of from 3×1013 cm?3 to 3×1014 cm?3, preparing a silicon substrate by machining the silicon crystal, and forming an epitaxial layer at the surface of the silicon substrate.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: August 14, 2012
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Timo Mueller, Atsushi Ikari, Wilfried von Ammon, Martin Weber
  • Patent number: 8231725
    Abstract: Semiconductor wafers of silicon are produced by pulling a single crystal growing on a phase boundary from a melt contained in a crucible and cutting of semiconductor wafers therefrom, wherein during pulling of the single crystal, heat is delivered to a center of the phase boundary and a radial profile of a ratio V/G from the center to an edge of the phase boundary is controlled, G being the temperature gradient perpendicular to the phase boundary and V being the pull rate. The radial profile of the ratio V/G is controlled so that the effect of thermomechanical stress in the single crystal adjoining the phase boundary, is compensated with respect to creation of intrinsic point defects. The invention also relates to defect-free semiconductor wafers of silicon, which can be produced economically by this method.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 31, 2012
    Assignee: Siltronic AG
    Inventors: Andreas Sattler, Wilfried von Ammon, Martin Weber, Walter Haeckl, Herbert Schmidt
  • Publication number: 20120190277
    Abstract: An insert carrier is configured to receive at least one semiconductor wafer for double-side processing of the wafer between two working disks of a lapping, grinding or polishing process. The insert carrier includes a core of a first material that has a first surface and a second surface, and at least one opening configured to receive a semiconductor wafer. A coating at least partially covers the first and second surfaces of the core. The coating includes a surface remote from the core that includes a structuring including elevations and depressions. A correlation length of the elevations and depressions is in a range of 0.5 mm to 25 mm and an aspect ratio of the structuring is in a range of 0.0004 to 0.4.
    Type: Application
    Filed: December 6, 2011
    Publication date: July 26, 2012
    Applicant: SILTRONIC AG
    Inventors: Georg Pietsch, Michael Kerstan
  • Publication number: 20120189777
    Abstract: A method provides a respective flat working layer on each of two working disks of a double-side processing apparatus including a ring-shaped upper working disk, a ring shaped lower working disk and a rolling apparatus that are rotatably mounted about an axis of symmetry of the double-side processing apparatus. The method includes applying a lower intermediate layer and upper intermediate layer on respective surfaces of the lower and upper working disks. Then, simultaneous leveling of both intermediate layers is performed by moving trimming apparatuses on cycloidal paths over the intermediate layers using the rolling apparatus and the respective outer toothing under pressure and with addition of a cooling lubricant, so as to provide a material removal from the intermediate layers. A lower working layer of uniform thickness is then applied to the lower intermediate layer and an upper working layer of uniform thickness is applied to the upper intermediate layer.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 26, 2012
    Applicant: SILTRONIC AG
    Inventor: Georg Pietsch
  • Patent number: 8221550
    Abstract: A process for producing a single crystal of semiconductor material, in which fractions of a melt, are kept in liquid form by a pulling coil, solidify on a seed crystal to form the growing single crystal, and granules are melted in order to maintain the growth of the single crystal. The melting granules are passed to the melt after a delay. There is also an apparatus which Is suitable for carrying out the process and has a device which delays mixing of the molten granules and of the melt.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: July 17, 2012
    Assignee: Siltronic AG
    Inventor: Wilfried von Ammon
  • Publication number: 20120178346
    Abstract: A method for cooling a cylindrical workpiece during wire sawing includes applying a liquid coolant to a surface of the workpiece. The workpiece is made of semiconductor material having a surface including two end faces and a lateral face. The method includes sawing the workpiece with a wire saw including a wire web having wire sections arranged in parallel by penetrating the wire sections into the workpiece by an oppositely directed relative movement of the wire sections and the workpiece. Wipers are disposed so as to bear on the surface of the workpiece. The temperature of the workpiece is controlled during the wire sawing using a liquid coolant applied onto the workpiece above the wipers so as to remove the liquid coolant with the wipers bearing on the workpiece surface.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 12, 2012
    Applicant: SILTRONIC AG
    Inventors: Peter Wiesner, Anton Huber
  • Patent number: 8216361
    Abstract: Monocrystalline semiconductor wafers have defect-reduced regions, the defect-reduced regions having a density of GOI-relevant defects within the range of 0/cm2 to 0.1/cm2 and occupy overall an areal proportion of 10% to 100% of the planar area of the semiconductor wafer, wherein the remaining regions of the semiconductor wafer have a significantly higher defect density than the defect-reduced regions. The wafers may be produced by a method for annealing GOI relevant defects in the wafer, by irradiating defined regions of a side of the semiconductor wafer by laser wherein each location is irradiated with a power density of 1 GW/m2 to 10 GW/m2 for at least 25 ms, wherein the laser emits radiation of a wavelength above the absorption edge of the wafer semiconductor material and wherein the temperature of the wafer rises by less than 20 K as a result of irradiation.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: July 10, 2012
    Assignee: Siltronic AG
    Inventors: Dieter Knerer, Andreas Huber, Ulrich Lambert, Friedrich Passek
  • Publication number: 20120160154
    Abstract: An ingot production method which makes it possible to greatly restrict formation of pinholes or substantially prevent them avoids the use of substantial amounts of small-sized polycrystalline silicon chunks of polycrystalline silicon chunks, only middle-sized polycrystalline silicon chunks and large-sized polycrystalline silicon chunks. In the step of filling polycrystalline silicon, the polycrystalline silicon chunks are randomly supplied into the crucible.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 28, 2012
    Applicant: SILTRONIC AG
    Inventors: Hideo Kato, Hideaki Murakami
  • Publication number: 20120160156
    Abstract: A method for recharging raw material polycrystalline silicon which enables large chunks of polycrystalline silicon to be recharged to a CZ ingot growth process while preventing the CZ crucible from being damaged and restricting a decline of the dislocation free rate and the quality of the grown ingot. Polycrystalline silicon chunks are recharged by first forming cushioning layer silicon of smaller chunks. The cushioning layer of polycrystalline silicon chunks are deposited on a surface of the residual silicon melt in a crucible. Subsequently, large-sized polycrystalline silicon chunks are introduced onto the cushioning layer, the cushioning layer cushioning the impact due to dropping of the large-sized polycrystalline silicon chunks.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 28, 2012
    Applicant: SILTRONIC AG
    Inventors: Hideo Kato, Satoko Yoshimura, Takeshi Ninomiya
  • Publication number: 20120152278
    Abstract: A method for cleaning a semiconductor wafer composed of silicon directly after a process of chemical mechanical polishing of the semiconductor wafer includes transferring the semiconductor wafer from a polishing plate to a first cleaning module and spraying both side surfaces of the semiconductor wafer with water at a pressure no greater than 1000 Pa at least once while transferring the semiconductor wafer. The semiconductor wafer is then cleaned between rotating rollers with water. The side surfaces of the semiconductor wafer are sprayed with an aqueous solution containing hydrogen fluoride and a surfactant at a pressure no greater than 70,000 Pa. Subsequently, the side surfaces are sprayed with water at a pressure no greater than 20,000 Pa. The wafer is then dipped into an aqueous alkaline cleaning solution, and then cleaned between rotating rollers with a supply of water. The semiconductor wafer is then sprayed with water and dried.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 21, 2012
    Applicant: SILTRONIC AG
    Inventor: Reinhold Lanz
  • Publication number: 20120156970
    Abstract: A method for the simultaneous material-removing processing of both sides of at least three semiconductor wafers includes providing a double-side processing apparatus including two rotating ring-shaped working disks and a rolling apparatus. The carriers are arranged in the double-side processing apparatus and the openings are disposed in the carriers so as to satisfy the inequality: R/e·sin(?/N*)?r/e?1?1.2 where N* denotes a ratio of the round angle and an angle at which adjacent carriers are inserted into the rolling apparatus with the greatest distance with respect to one another, r denotes a radius of each opening for receiving a respective semiconductor wafer, e denotes a radius of a pitch circle around a midpoint of the carrier on which the opening is arranged, and R denotes a radius of the pitch circle on which the carriers move between the working disks by means of the rolling apparatus.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 21, 2012
    Applicant: SILTRONIC AG
    Inventor: Georg Pietsch
  • Publication number: 20120149198
    Abstract: A method for producing a semiconductor wafer includes a number of steps in order including a bilateral material-removing process followed by rounding off an edge of the wafer and grinding front and back sides of the wafer by holding one side and grinding the other. The front and back are then polished with a polishing cloth including bound abrasives and subsequently treated with an etching medium to carry out a material removal of no more than 1?m on each side. The front side is then polished using a polishing cloth including bound abrasives and the back side is simultaneously polished using a polishing cloth free of abrasives while a polish with abrasives is provided. The edge is then polished followed by polishing the back with a polishing cloth including bound abrasives and simultaneously polishing the front with a cloth free of abrasives while a polish including abrasives is provided.
    Type: Application
    Filed: August 11, 2010
    Publication date: June 14, 2012
    Applicant: SILTRONIC AG
    Inventor: Juergen Schwandner
  • Patent number: 8197300
    Abstract: Correction of grinding spindle positions in double-side grinding machines for the simultaneous double-side machining of semiconductor wafers is achieved by torsionally coupling the two grinding spindles, each comprising a grinding disk flange for receiving a grinding disk, and providing a measuring unit with an inclinometer and two sensors for distance measurement, between the two grinding disk flanges such that the grinding spindles are essentially in the position they would have with mounted grinding disks during the grinding process, wherein the coupled grinding spindles are rotated while inclinometer and sensors determine radial and axial correction values of axial alignment to adjust the grinding spindles to a symmetrical orientation. The spindle positions may be corrected under the action of process forces.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: June 12, 2012
    Assignee: Siltronic AG
    Inventors: Joachim Junge, Robert Weiss
  • Patent number: 8197594
    Abstract: Silicon wafers having a density of BMDs with sizes between 20 to 40 nm at positions ?20 ?m below the wafer surface in the range of 5×1011/cm3, and a density of BMDs with sizes of ?300 nm?1×107/cm3, exhibit reduced slip dislocation and warpage. The wafers are sliced from a crystal grown under specific conditions and then subjected to both low temperature heat-treatment and high temperature anneal.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: June 12, 2012
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Wilfried von Ammon, Sei Fukushima, Herbert Schmidt, Martin Weber
  • Patent number: 8172941
    Abstract: Semiconductor wafers of silicon are produced by pulling a single crystal from a melt contained in a crucible and slicing semiconductor wafers from the pulled single crystal, heat being delivered to a center of the growing single crystal at the boundary with the melt during the pulling of the single crystal, a CUSP magnetic field applied such that a neutral surface of the CUSP magnetic field intersects a pulling axis of the single crystal at a distance of at least 50 mm from a surface of the melt. An apparatus suitable therefore contains a CUSP field positioned such that a neutral field intersects the axis of the crystal in the crucible 50 mm or more from the melt surface.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: May 8, 2012
    Assignee: Siltronic AG
    Inventors: Martin Weber, Herbert Schmidt, Wilfried von Ammon
  • Patent number: 8172943
    Abstract: Single crystalline ingots can be stably pulled free from dislocation and with a good crystal shape by actuating a crystal driving unit so as to immerse a seed crystal in a silicon melt, and controlling the crystal driving unit and a crucible driving unit under predetermined conditions so as to pull the seed crystal. During pulling, a horizontal magnetic field positioning device applies a magnetic field in the horizontal direction to the inside of the silicon melt, fixing the magnetic field axis at a constant position from the liquid surface of the melt. Positional adjustment of the vertical position of the horizontal magnetic field is performed in advance by a magnetic field position adjusting device, and the magnetic field axis of the applied field is fixed at a constant distance lower than the liquid surface of the melt by more than 50 mm and at the same level or higher than a depth L from the melt surface at the point of tail-in.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: May 8, 2012
    Assignee: Siltronic AG
    Inventor: Masamichi Ohkubo
  • Publication number: 20120098100
    Abstract: A support ring for supporting a monocrystalline silicon semiconductor wafer during a thermal treatment of the semiconductor wafer has outer and inner lateral surfaces and a curved surface extending from the outer lateral surface to the inner lateral surface, this curved surface serving for the placement of the semiconductor wafer. The curved surface has a radius of curvature of not less than 6000 mm and not more than 9000 mm for 300 mm diameter wafers, or a radius of curvature of not less than 9000 mm and not more than 14,000 mm for 450 mm diameter wafers. Use of the support ring during thermal treatment reduces slip and improves wafer nanotopography.
    Type: Application
    Filed: October 17, 2011
    Publication date: April 26, 2012
    Applicant: SILTRONIC AG
    Inventors: Erich Daub, Raimund Kaiss, Michael Kloesler, Thomas Loch
  • Patent number: 8157617
    Abstract: Semiconductor wafers are CMP polished by polishing the rear side of the semiconductor wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is higher at the center than at the edge of the rear side; and polishing the front side of the wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is lower in the center of the front side than in an edge region of the front side.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: April 17, 2012
    Assignee: Siltronic AG
    Inventors: Clemens Zapilko, Thomas Jaeschke, Makoto Tabata, Klaus Roettger