Abstract: Provided herein may be an error correction decoder based on an iterative decoding scheme using NB-LDPC codes and a memory system having the same. The error correction decoder may include a symbol generator for assigning an initial symbol to a variable node, a reliability value manager for setting and updating reliability values of candidate symbols of the variable node in current iteration, a flipping function value calculator for calculating a flipping function value by subtracting a function value, related to the updated reliability values of remaining candidate symbols other than a target candidate symbol, from another function value, related to the updated reliability value of the target candidate symbol, in the current iteration, and a symbol corrector for changing the hard decision value to the target candidate symbol when the flipping function value is equal to or greater than a first threshold value in the current iteration.
Abstract: Provided are devices having a device including a ramp signal generator which may comprise: a slope control circuit configured to generate a controllable analog reference voltage according to a digital setting code value to control a slope of a ramp signal; and at least one unit current cell configured to adjust the slope of the ramp signal by adjusting a current flowing through the at least one unit current cell according to the controllable analog reference voltage generated by the slope control circuit.
Abstract: A semiconductor memory device includes a controller for sequentially activating first and second control signals and activating a third control signal during an amplification period, in a pseudo cryogenic temperature, a first driver for driving a first power source line with a first voltage during an initial period of the amplification period, based on the first control signal, a second driver for driving the first power source line with a second voltage during a later period of the amplification period, based on the second control signal, a third driver for driving a second power source line with a third voltage during the amplification period, based on the third control signal, and a sense amplifier for primarily amplifying a voltage difference between a data line pair using the first and third voltages during the initial period, and secondarily amplifying the difference using the second and third voltages during the later period.
Abstract: A memory device, in accordance with a method of operation, may include: a plurality of pages coupled to a common word line and configured to be sequentially selected by different select lines; a program operation controller configured to perform a program operation on a first page that is to be programmed first, among the plurality of pages; and a start loop manager configured to generate start loop information about a program loop in which program verification corresponding to each of a plurality of program states to be formed by threshold voltages of memory cells included in the first page starts, during the program operation on the first page. The program operation controller is further configured to perform a program operation on a second page to be programmed subsequent to the first page, among the plurality of pages, based on the start loop information.
Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a memory block including a plurality of pages; a peripheral circuit for performing a first erase operation, a program operation, and a second erase operation on the memory block in a write operation on the memory block; and control logic for controlling the peripheral circuit to perform the write operation. The control logic is configured to control the peripheral circuit to erase a plurality of memory cells included in the memory block to a pre-erase state having a threshold voltage higher than a threshold voltage of a target erase state in the first erase operation, and controls the peripheral circuit to erase some memory cells among the plurality of memory cells to the target erase state in the second erase operation.
Abstract: A memory system may include a memory device comprising a plurality of memory blocks and a controller suitable for controlling an operation of the memory device. The controller may perform a fake operation on a predetermined memory block not used to store data when a temperature of the memory device is in a low temperature range.
Abstract: In a memory controller for controlling an operation of a memory device, the memory controller includes a buffer memory and a processor. The buffer memory stores first data received from a host and second data received from the memory device. The processor controls the memory controller to generate a write command for programming the first data and the second data to the memory device.
Abstract: A resistance variable memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and a selected memory cell. The write pulse control block may selectively enable any one of the high resistance path circuit and the bypass circuit in accordance with a position the selected memory cell.
Abstract: A memory system may include: a nonvolatile memory device including a plurality of memory blocks; and a controller for reading data stored in a physical address in response to a read command from a host, the read command including a first logical address, a first physical address corresponding to the first logical address, and a first read count associated with the first physical address, the controller may read first data from a first block corresponding to the first physical address and sends a response to the read command to the host, the response including the first data and updated information relating to the first read count.
Abstract: A derivative receiver includes a differentiator configured to differentiate an input signal; a comparator configured to produce a comparison signal by comparing a derivative signal produced using an output from the differentiator with a threshold voltage; and a pattern detecting equalizer configured to output a data signal by sampling an equalization signal generated by adjusting a level of the comparison signal. The level of the comparison signal is adjusted according to a past value of the data signal.
May 11, 2020
Date of Patent:
June 8, 2021
SK hynix Inc., Seoul National University R&DB Foundation
Abstract: A semiconductor device includes a buffer control circuit and an operation control circuit. The buffer control circuit generates an enable signal based on a self-refresh signal and to generate an end control signal and a supply control signal from a first internal chip selection signal during a self-refresh operation. The operation control circuit generates a frequency information signal from an internal command/address signal when an update signal is inputted during a mode register write operation, adjusts a shift amount based on the frequency information signal when the supply control signal is inputted during the mode register write operation, and generates an internal write command according to the adjusted shift amount during a read-modify-write operation in synchronization with an internal clock signal after generating an internal read command.
Abstract: The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of memory blocks, the memory device configure to perform on each of the plurality of memory blocks at least one of a program operation, a read operation, or an erase operation in response to an internal command; and a controller in communication with a host and the memory device and configured to receive a request from the host and generate the internal command in response to the request from the host, the controller further configured to control the memory device to perform a stress check operation on a first memory block of the plurality of memory blocks in which the program operation has been completed.
October 28, 2019
Date of Patent:
June 8, 2021
SK hynix Inc.
Min Ho Her, Sung Ho Kim, Seung Il Kim, Jae Min Lee
Abstract: The present technology includes a controller including an allocation manager configured to determine whether a host identification (ID) output from a host is an allocable ID, an address manager configured to perform an allocation operation using the host ID to select logical blocks corresponding to the host ID when the host ID is received from the allocation manager, and output an address of the logical blocks as an allocation address, and a map table component configured to store a map table in which logical block addresses and physical block addresses are respectively mapped, select a logical block address corresponding to the allocation address, and output the physical block address mapped to the selected logical block address, a memory system including the controller, and a method of operating the memory system.
Abstract: A memory device includes a write error check circuit suitable for detecting an error in received data using an error correction code during a write operation; and a memory core suitable for storing the received data and the received error correction code when no error is detected by the write error check circuit.
July 5, 2018
Date of Patent:
June 8, 2021
SK hynix Inc.
Hoiju Chung, Young-Do Hur, Hyuk Lee, Jang-Ryul Kim
Abstract: A data storage apparatus includes a nonvolatile memory device including a plurality of memory blocks in which a plurality of word lines to which one or more pages are coupled are arranged, a data buffer configured to buffer data to be stored in the one or more pages of the nonvolatile memory device, and a processor configured to detect, when a sudden power off (SPO) occurs, one or more first pages in which an interference has occurred in a memory block in use and store data corresponding to the one or more first pages in which the interference has occurred among the data buffered in the data buffer in a backup memory block of the nonvolatile memory device.
Abstract: A memory system includes a nonvolatile memory device including a plurality of dies, each die including a plurality of planes, each plane including a plurality of blocks, each block including a plurality of pages, and further includes a plurality of page buffers, each page buffer for caching data in a unit of a page to be inputted to, and outputted from, each of the blocks; and a controller suitable for managing a plurality of super blocks according to a condition, each super block including N blocks capable of being read in parallel among the blocks, generating predicted required times for the super blocks, respectively, each of the predicted required times representing a time needed to extract valid data from the corresponding super block, and selecting a victim block for garbage collection from among the blocks based on the predicted required times.
Abstract: A memory device may include a clock dividing circuit suitable for generating a plurality of internal clocks by dividing an external clock, a mode decision circuit suitable for determining an operation mode according to an input time point of a read command based on the internal clocks, a clock arranging circuit suitable for arranging the internal clocks in an order determined according to the operation mode, and outputting the arranged clocks as a plurality of data output clocks, and a data arranging circuit suitable for arranging read data according to the operation mode, and outputting the arranged data in response to the data output clocks.
Abstract: A Processing-In-Memory (PIM) device includes an error correction code (ECC) logic circuit and an error accumulation detection circuit. The error correction code (ECC) logic circuit configured to detect an erroneous bits included in first data to generate a parity bit, and to detect an error correction capability of the first data to generate an error correction fail signal. The error accumulation detection circuit configured to generate an error accumulation signal counted by a pulse of the error correction fail signal. The error correction capability set to the maximum number of erroneous bits that can be corrected by performing an ECC operation on the first data.
Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.
February 11, 2021
June 3, 2021
SK hynix Inc.
Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK
Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device includes a memory cell, a page buffer coupled to the memory cell through a bit line and configured to perform a read operation of sensing data stored in the memory cell, wherein the page buffer includes a data storage configured to store data sensed from the memory cell, the read operation includes a precharge period during which a precharge voltage is applied to the bit line, an evaluation period during which a state of the memory cell is incorporated into a voltage of the bit line, and a data storage period during which the data sensed through the bit line is stored in the data storage, and the data storage is initialized during the evaluation period.