Patents Assigned to SK Hynix Inc.
  • Publication number: 20220197596
    Abstract: A processing-in-memory (PIM) device includes a plurality of memory banks and a plurality of multiplication and accumulation (MAC) operators. The plurality of memory banks include a plurality of even memory banks and a plurality of odd memory banks. The plurality of MAC operators include a first MAC operator configured to be shared by a first even memory bank among the plurality of even memory banks and a first odd memory bank among the plurality of odd memory banks. The first MAC operator is configured to alternately perform an even MAC operation and an odd MAC operation.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 23, 2022
    Applicant: SK hynix Inc.
    Inventor: Choung Ki Song
  • Publication number: 20220199135
    Abstract: The present disclosure relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a word line, a first select line on the word line, a second select line on the first select line, a first upper contact extending to be in contact with a first surface of the first select line, and a second upper contact extending through the second select line to be in contact with a second surface of the first select line, wherein the first surface and the second surface of the first select line are on opposites sides of each other.
    Type: Application
    Filed: June 28, 2021
    Publication date: June 23, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20220197543
    Abstract: A method for assigning a plurality of channel of a storage device for stream data writing, a storage device and a storage medium are provided. The method includes: providing global available channel status data and stream suitable channel status data for one of a plurality of streams by a controller of the storage device for processing stream data writing for the plurality of streams; generating stream available channel status data for the one of the plurality of streams, based on the global available channel status data and the stream suitable channel status data for the stream; selecting at least one available channel of the plurality of channels according to the stream available channel status data; and updating the global available channel status data with respect to the at least one available channel selected and updating the stream suitable channel status data for one of the plurality of streams.
    Type: Application
    Filed: November 18, 2021
    Publication date: June 23, 2022
    Applicant: SK hynix Inc.
    Inventors: CHING-CHUNG LAI, LIAN-CHUN LEE, CHUN-SHU CHEN
  • Publication number: 20220199136
    Abstract: In general, according to one embodiment, a magnetoresistance memory device includes: a first ferromagnetic layer; an insulating layer above the first ferromagnetic layer; a second ferromagnetic layer above the insulating layer; a third ferromagnetic layer above the second ferromagnetic layer; and a fourth ferromagnetic layer above the third ferromagnetic layer. The third ferromagnetic layer includes an oxide of an alloy including iron. The fourth ferromagnetic layer includes iron and a 5d transition metal.
    Type: Application
    Filed: July 30, 2021
    Publication date: June 23, 2022
    Applicants: Kioxia Corporation, SK hynix Inc.
    Inventors: Taiga ISODA, Young Min EEH, Tadaaki OIKAWA, Eiji KITAGAWA, Kazuya SAWADA, Jin Won JUNG, Jung Hyeok KWAK
  • Patent number: 11367685
    Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventors: Seong-Hyun Kim, Jung-Won Seo, An-Na Choi
  • Patent number: 11367732
    Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a logic circuit, and a second chip stacked on the first chip and configured to include a memory cell array. At least one transfer circuit for connecting a row line of the memory cell array to a global row line is distributed to each of the first chip and the second chip.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Go Hyun Lee
  • Patent number: 11366611
    Abstract: A data processing system may include: a host suitable for including a first physical address corresponding to a first logical address in a first command, wherein the first physical address and the first logical address are associated with data, and sending the first command with the first physical address; and a memory system suitable for performing an operation corresponding to the first command by using the first physical address received from the host, and sending a result of the performed command operation to the host as a response, the host may check a time difference between a first time point that the first command is sent and a second time point that the response corresponding to the first command is received, and may determine whether to use the first physical address in a next command, based on a result of the time difference check.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11367505
    Abstract: The present technology relates to an electronic device. According to the present technology, a memory device having reduced latency includes a plurality of memory cells, an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value, which is the number of memory cells read as a first memory cell based on data read from the plurality of memory cells among the plurality of memory cells, and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on the data read from the plurality of memory cells using the default read voltage, in response to an optimum read voltage setting command input from a memory controller, and generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Byoung Sung You
  • Patent number: 11366736
    Abstract: A memory system includes a nonvolatile memory device; a random access memory configured to store, in response to an unmap request received from a host device, a flag information indicating that an unmap address as a target of the unmap request is unmapped; and a control unit configured to flush the flag information to the nonvolatile memory device, wherein the control unit flushes the flag information to the nonvolatile memory device when a first condition is satisfied.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventors: Byeong Gyu Park, Ik Sung Oh, Seung Gu Ji, Sung Kwan Hong
  • Patent number: 11366725
    Abstract: The present technology relates to an electronic device. A storage device according to the present technology includes a memory device including a plurality of logical storage areas, and a memory controller. The memory controller controls the memory device to perform a memory operation on an original storage area of the plurality of logical storage areas according to a request of a host, and to perform a mirroring operation of copying the memory operation which was performed on the original storage area in a backup storage area of the plurality of logical storage areas based on whether the memory device is in an idle state.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyeong Jae Choi
  • Patent number: 11366718
    Abstract: A memory system includes a memory device including a plurality of cells associated with multiple pages and a controller. The controller selects a read bias set in response to a read address and modifies the read bias set to generate modified read bias set using one of a plurality of modification arrays. The controller performs a read operation on the select page using the modified read bias set. For a select read bias of the read bias set, the controller accumulates a fail bit count corresponding to a read operation using a select modified read bias of the modified read bias set into the plurality of accumulators using subtraction or addition. When an absolute value of a certain accumulator of the fail bit count is greater than a threshold, the controller shifts the select read bias in a correction direction by a specific magnitude corresponding to the accumulator sign.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Teodor Vlasov
  • Patent number: 11367504
    Abstract: A semiconductor memory device includes a plurality of planes defined in a plurality of chip regions; and a rescue circuit configured to disable a failed plane and enable a normal plane from among the plurality of planes, wherein the semiconductor memory device operates with only normal planes that are enabled.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Lae Oh
  • Patent number: 11366733
    Abstract: A method for controlling temperature of a memory system which includes a memory device suitable for storing memory map data including a logical address of an external device and a physical address of a memory device, corresponding to the logical address; and a controller suitable for downloading at least a part of the memory map data and storing and managing the downloaded data as controller map data, and uploading at least a part of the controller map data to the external device, the method comprising: measuring temperature of the memory device; and performing a map downloading for the memory map data from the memory device in response to the measured temperature.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Byung-Jun Kim
  • Patent number: 11367492
    Abstract: An electronic device is provided. A page buffer includes at least one data latch, a sensing latch, and a bit line voltage controller. At least one data latch stores a program verification result of a previous program loop among a plurality of program loops and program data to be stored in a memory cell. The sensing latch stores a program verification result of a current program loop among the plurality of program loops. The bit line voltage controller updates the program verification result of the previous program loop which is stored in the at least one data latch to the sensing latch during a program operation of a next program loop of the current program loop among the plurality of program loops.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11366763
    Abstract: A controller, a memory system and an operating method thereof are disclosed. The controller controls a nonvolatile memory device and the nonvolatile memory includes a first memory module configured to store a plurality of pieces of map data read from the nonvolatile memory device; and a second memory module configured to cache map data having locality among map data received from the first memory module.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Do Hun Kim
  • Patent number: 11367503
    Abstract: The present technology includes a method of operating a controller that controls a semiconductor memory device including a plurality of memory blocks. The method includes receiving a read request for data included in any one memory block among the plurality of memory blocks from a host, and controlling the semiconductor memory device to read data corresponding to the read request using a read-history table. The read-history table includes read voltages used for a plurality of read pass operations for the any one memory block, respectively.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Jin Sub Kim
  • Patent number: 11367488
    Abstract: A memory system includes a memory device and a controller. The controller determines a target word line group to which a target word line corresponding to a read command belongs. The controller identifies a reference voltage corresponding to the target word line group. The controller controls the memory device to perform a read operation on a target page coupled to the target word line, using the reference voltage.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventors: Aman Bhatia, Chenrong Xiong, Fan Zhang, Naveen Kumar, Xuanxuan Lu, Yu Cai
  • Patent number: 11367467
    Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyung Sik Won, Seung Han Oak, Jun Phyo Lee
  • Publication number: 20220189534
    Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.
    Type: Application
    Filed: November 8, 2021
    Publication date: June 16, 2022
    Applicant: SK hynix Inc.
    Inventors: Jeong Jin HWANG, Sung Nyou YU, Duck Hwa HONG, Sang Ah HYUN, Soo Hwan KIM
  • Publication number: 20220189978
    Abstract: There are provided a semiconductor memory device and a method of manufacturing a semiconductor memory device. The semiconductor memory device includes a conductive pattern, an etch stop layer on the conductive pattern, a conductive bonding pattern including a contact portion connected to the conductive pattern, and a pad portion extending from the contact portion, a first dielectric layer disposed on the etch stop layer and spaced apart from the conductive bonding pattern, and a second dielectric layer including a first portion surrounding a sidewall of the contact portion of the conductive bonding pattern between the pad portion of the conductive bonding pattern and the etch stop layer, and a second portion extending from the first portion to cover an upper surface of the first dielectric layer.
    Type: Application
    Filed: June 24, 2021
    Publication date: June 16, 2022
    Applicant: SK hynix Inc.
    Inventors: Jae Young OH, Nam Jae LEE