Patents Assigned to SK Hynix Inc.
  • Publication number: 20240089886
    Abstract: A method for lane synchronization for an interconnection protocol, a controller, and a storage device. The method is suitable for a first device capable of linking to a second device according to the interconnection protocol, and includes providing data representing a de-skew interval which indicates a time interval between two consecutive periodic de-skew patterns. Then performing, by a hardware protocol engine for implementing a link layer of the interconnection protocol, a periodic de-skew pattern transmission adaptively over lanes from the first device to the second device according to the de-skew interval and in response to communication status information between the first device and the second device. The hardware protocol engine is configured to send a de-skew pattern periodically according to the de-skew interval when the communication status information satisfies a criterion, and to postpone sending of the de-skew pattern when the communication status information does not satisfy the criterion.
    Type: Application
    Filed: October 24, 2022
    Publication date: March 14, 2024
    Applicant: SK hynix Inc.
    Inventor: FU HSIUNG LIN
  • Publication number: 20240090214
    Abstract: Provided herein are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a lower substrate, a peripheral circuit component located on the lower substrate, a lower bonding layer including a lower capacitor structure, the capacitor structure located on the peripheral circuit component, an upper bonding layer including an upper capacitor structure, the upper bonding layer bonded to the lower bonding layer, a plurality of cells and a dummy insulating layer that are located on the upper bonding layer, and an upper substrate being located on the plurality of cells and the dummy insulating layer, wherein the upper capacitor structure is coupled to the lower capacitor structure.
    Type: Application
    Filed: March 3, 2023
    Publication date: March 14, 2024
    Applicant: SK hynix Inc.
    Inventor: Jae Taek KIM
  • Publication number: 20240087982
    Abstract: A semiconductor module includes a semiconductor module body and a guide. The semiconductor module body extends in a first direction and a second direction intersecting the first direction. A plurality of connection terminals is arranged at one end of the semiconductor module in the second direction. A plurality of semiconductor devices is arranged on at least one side of the semiconductor module body. The guide is arranged at the other end of the semiconductor module body opposite to the one end to induce a flow of a cooling fluid toward the one end of the semiconductor module.
    Type: Application
    Filed: February 2, 2023
    Publication date: March 14, 2024
    Applicant: SK hynix Inc.
    Inventors: Nam Hyeon CHOI, Seung Jin RYU
  • Publication number: 20240085939
    Abstract: A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 14, 2024
    Applicant: SK hynix Inc.
    Inventors: Yeon Ho LEE, Yong Suk CHOI
  • Publication number: 20240088021
    Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: SK hynix Inc.
    Inventors: Jae Yoon NOH, Tae Kyung KIM, Hyo Sub YEOM, Jeong Yun LEE
  • Publication number: 20240089595
    Abstract: Disclosed is an image sensor including a pixel array having a pixel pattern in which first to fourth 2×2 pixel groups are arranged in a clockwise direction, one infrared pixel is arranged in each of two 2×2 pixel groups that are not adjacent to each other, the same green pixels are arranged in a first diagonal direction, and red pixels and blue pixels are arranged in half in a second diagonal direction crossing the first diagonal direction, in a 4×4 unit pixel group.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 14, 2024
    Applicant: SK hynix Inc.
    Inventor: Su Ram CHA
  • Patent number: 11927623
    Abstract: A semiconductor test device may include a chamber, a plurality of slots, a plurality of test boards and a plurality of temperature control modules. The slots may be arranged in the chamber. The test boards may be inserted into a part of the slots. The test boards may be configured to receive a plurality of semiconductor devices. The temperature control modules and the test boards may be alternately inserted into other parts of the slots. The temperature control modules may be configured to provide each of the test boards with air having a set temperature.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventor: Nack Hyun Kim
  • Patent number: 11928070
    Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventors: Yong Tae Jeon, Byung Cheol Kang, Seung Duk Cho, Sang Hyun Yoon, Se Hyeon Han, Jae Young Jang
  • Patent number: 11928362
    Abstract: A fuse latch of a semiconductor device including PMOS transistors and NMOS transistors includes a data transmission circuit configured to transmit data to a first node and a second node in response to a first control signal, a latch circuit configured to latch the data received from the data transmission circuit through the first node and the second node, and a data output circuit configured to output the data latched by the latch circuit in response to a second control signal. NMOS transistors contained in the data transmission circuit, the latch circuit, and the data output circuit may be formed in first, fourth, and fifth active regions, PMOS transistors are formed in second and third active regions, and the first to fifth active regions are sequentially arranged in a first direction.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: March 12, 2024
    Assignee: SK hynix inc.
    Inventors: Jae Hwan Seo, Chul Moon Jung
  • Patent number: 11928077
    Abstract: A data processing circuit includes a plurality of transformation blocks suitable for respectively transforming in parallel a plurality of input bit groups into a plurality of output bit groups, wherein each of the transformation blocks transforms a corresponding input bit group into a corresponding output bit group by using a random pattern.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventor: Kyoung Lae Cho
  • Patent number: 11928026
    Abstract: A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventors: Munseon Jang, Hoi Ju Chung, Jang Ryul Kim
  • Patent number: 11929279
    Abstract: A semiconductor device including: a trench defining an active region in a substrate; a first semiconductor liner formed over the trench; a second semiconductor liner formed over the first semiconductor liner; and a device isolation layer formed over the second semiconductor liner and filling the trench. Disclosed is also a method for fabricating a semiconductor device, the method including: forming a trench defining an active region in a substrate; forming a plurality of semiconductor liners over the trench; performing pretreatment before forming each of the semiconductor liners; and performing post-treatment after forming each of the semiconductor liners.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventor: Jin Woong Kim
  • Patent number: 11928056
    Abstract: The present technology relates to an electronic device. A memory controller that increases a hit ratio of a cache memory includes a memory buffer configured to store command data corresponding to a request received from a host, and a cache memory configured to cache the command data. The cache memory stores the command data by allocating cache lines based on a component that outputs the command data and a flag included in the command data.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventor: Do Hun Kim
  • Patent number: 11929122
    Abstract: A memory device includes plural non-volatile memory cells and a control circuit. The plural non-volatile memory cells can store data and are arranged in series between a bit line and a source line. The control circuit synchronizes discharge of charges, which are accumulated in a channel formed by the plural non-volatile memory cells, through the bit line and the source line during an erase operation for erasing the data stored in the plural non-volatile memory cells.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventor: Tae Heui Kwon
  • Patent number: 11929126
    Abstract: A memory device, and a method of operating the memory device, includes a memory block in which a plurality of cell pages are coupled to each of word lines. The memory device also includes a peripheral circuit configured to adjust a time point at which a verify voltage is applied to a selected word line among the word lines according to an order of performing a program operation during a verify operation of a selected cell page. The memory device further includes a control logic circuit configured to transmit, to the peripheral circuit, an operation code for adjusting a time point at which the verify voltage is output.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventors: Sung Hyun Hwang, Jae Yeop Jung, Se Chun Park
  • Patent number: 11929336
    Abstract: A semiconductor device includes a first pad defined on one surface of a first chip; a second pad defined on one surface of a second chip which is stacked on the first chip, and bonded to the first pad; a first resistor element defined in the first chip, and coupled to the first pad; and a second resistor element defined in the second chip, and coupled to the second pad.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: March 12, 2024
    Assignee: SK hynix inc.
    Inventor: Chan Ho Yoon
  • Patent number: 11928575
    Abstract: An activation function processing method includes processing a first activation function in a first mode by referring to a shared lookup table that includes a plurality of function values of the first activation function; and processing a second activation function in a second mode by referring to the shared lookup table, the second activation function being a different function than the first activation function.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventors: Yong Sang Park, Joo Young Kim
  • Patent number: 11929410
    Abstract: A method for fabricating a semiconductor device includes: providing a substrate having a front surface and a rear surface opposite to the front surface; forming a trench in the front surface of the substrate; forming a gate dielectric layer over the trench; forming a gate electrode that fills a bottom portion of the trench over the gate dielectric layer; forming a sealing layer that includes a first portion covering the gate electrode, the gate dielectric layer, and the front surface of the substrate, and a second portion covering the rear surface of the substrate; selectively removing the second portion of the sealing layer; and performing an annealing process to form a hydrogen treated surface on an interface between the trench and the gate dielectric layer.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventor: Jin Woong Kim
  • Patent number: 11928892
    Abstract: Methods for operating a motion recognition apparatus are disclosed. In some implementations, a method for recognizing a motion or gesture of an object may include operating an optical sensor device to capture light reflected from the object under illumination by light emitted toward the object, generating, by comparing the emitted light to the reflected light, a depth image including distance information indicating a distance between the optical sensor device and the object, generating, based on the light reflected from the object, an infrared image including infrared image information associated with the object, and determining the motion of the object based on at least one of the depth image and the infrared image.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: March 12, 2024
    Assignee: SK HYNIX INC.
    Inventor: Jae Hyung Jang
  • Patent number: 11929362
    Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, an active well, an emitter, a base, a collector, a body contact region, and a blocking well. The semiconductor substrate may have a first conductive type. The active well may be formed in the semiconductor substrate. The active well may have a second conductive type. The emitter and the base may be formed in the active well. The collector may be formed in the semiconductor substrate outside the active well. The body contact region may be formed in the semiconductor substrate to electrically connect the collector with the semiconductor substrate. The body contact region may have a conductive type substantially the same as that of the collector. The blocking well may be configured to surround an outer wall of the body contact region. The blocking well may have the second conductive type.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventors: Joung Cheul Choi, Jae Young You