Abstract: A semiconductor device including bumps and a method of manufacturing the same. The semiconductor device includes a first pillar and a second pillar formed over a substrate, a first solder layer configured to cover a first surface of the first pillar, and a second solder layer configured to cover a second surface of the second pillar. The first surface of the first pillar has a lower height than a height of the second surface of the second pillar. The second solder layer has a smaller thickness than a thickness of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface.

Abstract: A transmission and reception system includes a transmission circuit and a reception circuit. The transmission circuit is configured to generate a transmission signal based on an input signal. The reception circuit is configured to generate an output signal based on the transmission signal. The transmission circuit is configured to provide a duty cycle offset which is complementary with a duty cycle offset of the reception circuit.

Abstract: A transmission circuit includes a plurality of driving units coupled with an input/output pad. The transmission circuit performs a data transmission operation by selecting at least one main driving unit corresponding to a predetermined driving strength from among the plurality of driving units and performs an equalization operation by selecting at least one auxiliary driving unit from among remaining driving units excluding the main driving unit.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.

Abstract: There is provided a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first gate stacked body including a first channel hole, a second gate stacked body overlapping the first gate stacked body and including a second channel hole, a first memory layer extending along an inner wall of the first channel hole, a second memory layer extending along an inner wall of the second channel hole and including an end protruding into the first channel hole.

Abstract: A memory device and a method of operating the same are provided. The memory device may include a memory block including a plurality of memory cells, peripheral circuits configured to perform an erase operation including a gate induced drain leakage (GIDL) current generation operation and a data erase operation using an GIDL current on the memory block, and control logic configured to control the peripheral circuits to perform the erase operation, wherein the control logic is configured to control the peripheral circuits to apply a negative voltage to word lines of the memory block during the GIDL current generation operation.

Abstract: A polishing composition for a semiconductor process according to one embodiment of the present disclosure includes a polishing particle and a corrosion inhibitor. The corrosion inhibitor includes a first corrosion inhibitor, which is an amino azole-based compound and a second corrosion inhibitor, which is a diazole-based compound. The polishing composition for a semiconductor process has a pH of 2 to 5. A static etch rate for a tungsten film of the polishing composition for a semiconductor process is 6 ?/min or less. When polishing a substrate comprising a tungsten film and the silicon oxide film, such a polishing composition may provide a defect-reduced polished surface while exhibiting excellent polishing rate for a silicon oxide film.

Abstract: A semiconductor apparatus includes an internal voltage generation circuit and a control circuit. The internal voltage generation circuit includes a plurality of sub-circuits that receive an external voltage as an input and generate at least one internal voltage based on the external voltage. The control circuit determines where the external voltage falls within a range between a minimum operating voltage and a target operating voltage according to power information and a built-in lookup table and controls the plurality of sub-circuits according to a result of the determination.

Abstract: A semiconductor package includes a bonding wire which is connected to a semiconductor chip. A first encapsulation layer which surrounds the bonding wire is disposed. A second encapsulation layer which surrounds the first encapsulation layer is disposed. A surface roughness of the first encapsulation layer is less than that of the second encapsulation layer. A landing pad which contacts the bonding wire is disposed.

Abstract: There is provided a semiconductor memory device including: a substrate having a Complementary Metal Oxide Semiconductor (CMOS) circuit; a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on the substrate; a channel structure having a first part penetrating the gate stack structure and a second part extending from one end of the first part, the second part extending beyond the gate stack structure; a common source line extending to overlap with the gate stack structure, the common source line surrounding the second part of the channel structure; a memory layer disposed between the first part of the channel structure and the gate stack structure; and a bit line connected to the other end of the first part of the channel structure, the bit line being disposed between the substrate and the gate stack structure.

Abstract: A polishing composition for a semiconductor process includes polishing particles, a polishing pad protectant, and a fluorinated surfactant. The polishing composition for the semiconductor process has an Rm/e value of 2.5% or less, which is a ratio of a number of defects derived from an organic substance as calculated by Equation 1 below. Rm / e = Dm De × 100 ? ( % ) [ Equation ? 1 ] In the Equation 1, a De value is a number of defects detected from a top surface of a substrate after polishing the top surface with the polishing composition for the semiconductor process and etching back the top surface, and a Dm value is a number of defects derived from the organic substance among 100 defects randomly selected from the defects detected from the top surface after the polishing and etching back of the top surface. In these cases, polished and etched surfaces can prevent contamination by particles, especially organic particles.

Abstract: Disclosed is a semiconductor integrated circuit comprising a master chip including a first buffer circuit coupled to a first power line that is supplied with a first voltage and a first supply circuit that supplies a second voltage, having a lower voltage level than the first voltage, to a first through line in response to a control signal, and a slave chip, coupled to the first through line, including a second buffer circuit coupled to a second power line supplied with the second voltage and a second supply circuit that supplies the second voltage to a second through line in response to the control signal, which indicates whether the master chip and the slave chip are stacked.

Abstract: A clock generating circuit includes a first division circuit and a second division circuit. The first division circuit is configured to generate a first group of internal clock signals by dividing a clock signal. The second division circuit is configured to generate a second group of internal clock signals by dividing a delayed clock signal, the delayed clock signal generated by an internal circuit delaying the clock signal. An operation timing of the second division circuit can be adjusted based on one of the first group of internal clock signals generated by the first division circuit.

Abstract: A semiconductor memory device, and a method of operating the same, includes a memory block including a plurality of pages, a read and write circuit configured to apply a first bit line voltage to a selected bit line corresponding to a selected memory cell and apply a second bit line voltage having a potential lower than that of the first bit line voltage to an unselected bit line during detrap operation, a voltage generation circuit configured to generate a first set voltage, a second set voltage, and a pass voltage during the detrap operation, and an address decoder configured to apply the first set voltage to a selected word line corresponding to the selected page and apply the second set voltage having a potential higher than that of the first set voltage to unselected word lines, during the detrap operation.

Abstract: A memory device includes a precharge time information storage for storing information on a first precharge time for which a bit line control signal is applied and a second precharge time for which a source line control signal is applied, which are determined according to a degree to which a program operation is performed. The memory device also includes a precharge voltage controller for providing the bit line control signal and the source line control signal respectively to page buffers and a source line driver for a longer precharge time selected from the first precharge time and the second precharge time in the program operation.

Abstract: A bit-flipping (BF) decoder and a decoding method based on a super node, which groups two or more component nodes corresponding to two or more bits in a codeword to generate a super node; and performs a decoding iteration on the super node. The decoding iteration includes: calculating a flipping energy for the super node based on a flipping energy for each of the component nodes and internal checks between the component nodes; and flipping at least one of the two or more bits in the super node upon a determination that the flipping energy for the super node exceeds a bit-flipping threshold.

Abstract: A memory device includes a memory cell array including a plurality of memory cells; a sense amplifying circuit configured to sense data of the memory cells through bit lines, the sense amplifying circuit including: a first operational circuit configured to perform a first operation according to a first sensing control signal; and a second operational circuit configured to perform a second operation according to a second sensing control signal; and an operational monitoring circuit configured to provide the first sensing control signal or the second sensing control signal by monitoring whether at least some of the memory cells have a ferroelectric property.

Abstract: Provided herein is a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a contact pattern including a vertical contact part, and a sidewall contact part extending from the vertical contact part in a direction crossing the vertical contact part, a lower conductive pattern having a hole into which the vertical contact part is inserted, and an upper conductive pattern overlapping a portion of the lower conductive pattern. The upper conductive pattern includes a first side portion in contact with the sidewall contact part, and a second side portion facing the vertical contact part and spaced apart from the vertical contact part.

Abstract: A storage device may store temperature log information in one or more log memory blocks according to a temperature storage level and determine the temperature storage level based on a temperature change amount over time of a temperature of the storage device. By storing the temperature log information less frequently when smaller changes in the temperature are expected than when larger changes are, efficiency of storing the temperature log information may be improved.

Abstract: A memory device includes plural memory cells and control circuitry. Each of the memory cells is capable of storing multi-bit data corresponding to an erase state and plural program states. The control circuitry is configured to divide plural program loops, which are performed to store the multi-bit data in the plural memory cells, into plural program groups and apply different program pulses, which correspond to each of the plural program groups, to the plural memory cells.