Patents Assigned to SK Hynix Inc.
  • Publication number: 20190189240
    Abstract: A semiconductor apparatus may include a repair circuit configured to activate a redundant line of a cell array region by comparing repair information and address information. The semiconductor apparatus may include a main decoder configured to perform a normal access to the cell array region by decoding the address information. The address information may include both column information and row information.
    Type: Application
    Filed: June 1, 2018
    Publication date: June 20, 2019
    Applicant: SK hynix Inc.
    Inventor: Dong Keun KIM
  • Publication number: 20190187927
    Abstract: A buffer system may include a buffer configured to receive input data having an assigned priority level, store the input data within a memory stack regardless of the priority level assigned to the input data, and sequentially output the input data stored in the memory stack in order of the priority levels assigned to the input data.
    Type: Application
    Filed: June 8, 2018
    Publication date: June 20, 2019
    Applicant: SK hynix Inc.
    Inventors: Seunggyu JEONG, Jung Hyun KWON, Wongyu SHIN, Do-Sun HONG
  • Publication number: 20190189170
    Abstract: A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.
    Type: Application
    Filed: February 25, 2019
    Publication date: June 20, 2019
    Applicant: SK hynix Inc.
    Inventors: Hak Song KIM, Min Su PARK
  • Publication number: 20190189205
    Abstract: A resistive memory apparatus includes a memory cell array, a local switch, and a global switch. The memory cell array may include a plurality of resistive memory cells coupled to a plurality of connection lines. The local switch may select a target connection line coupled to a target memory cell and a preset number of connection lines adjacent to the target connection line according to a signal obtained by decoding an address. The global switch may apply a preset level of voltage to the selected adjacent connection lines according to the signal obtained by decoding the address.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 20, 2019
    Applicant: SK hynix Inc.
    Inventors: Jeong Ho YI, Min Chul SHIN
  • Patent number: 10325846
    Abstract: A fuse structure may include an anode pattern, a cathode pattern and a connection member. The anode pattern may be formed on a semiconductor substrate. The cathode pattern may be formed on the anode pattern. The connection member may be electrically connected between the anode pattern and the cathode pattern. The connection member may have different widths.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventor: Dong Yean Oh
  • Patent number: 10324630
    Abstract: A memory system includes a controller and a plurality of nonvolatile memories; a temperature control unit suitable for measuring a temperature of each of the plurality of nonvolatile memories, and comparing each measured temperature with a predetermined threshold value; a signal generation unit generating busy signals corresponding to one or more of the nonvolatile memories when the measured temperature is higher than the predetermined threshold value; and an interface unit transmitting the busy signal to the controller.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Duck-Hoi Koo, Yong Jin
  • Patent number: 10324573
    Abstract: A sensing device may include an integrator configured to sense electrical characteristics of first and second nodes to generate an output voltage. A sensing device may include a switching portion configured to include a plurality of switches, wherein the plurality of switches operate to connect at least one of the plurality of switches to the first node and to connect the remaining switches of the plurality of switches to the second node during each of a plurality of successive switching cycles.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventor: Keunjin Chang
  • Patent number: 10325654
    Abstract: A resistive memory device and a fabricating method thereof are provided. The resistive memory device includes: a first electrode electrically coupled with a first wire; a second electrode facing the first electrode and electrically coupled with a second wire, the second electrode including an oxygen vacancy reservoir and a contact electrode, and a memory cell including a variable resistive layer and being disposed between the first electrode and the second electrode. The variable resistive layer has a conductive filament, which includes oxygen vacancies and connects the first electrode and the second electrode. The oxygen vacancy reservoir is disposed on the variable resistive layer, and the contact electrode is coupled to the oxygen vacancy reservoir and the second wire. The oxygen vacancy reservoir has a volume or oxidizing power to exchange a limited amount of oxygen ions and oxygen vacancies required for switching the conductive filament with the variable resistive layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 18, 2019
    Assignees: Seoul National University R&DB Foundation, SK hynix Inc.
    Inventors: Cheol Seong Hwang, Jaeyeon Lee
  • Patent number: 10325669
    Abstract: An error information storage circuit configured to write information stored in a plurality of fuse sets to a plurality of fuse latch sets of a core block and/or to write test data to the plurality of fuse latch sets. The test data is internally generated depending on a fuse clock signal, and the test data has values which cause opposite levels to be written in adjacent latches of the plurality of fuse latch sets.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong Sam Kim
  • Patent number: 10325924
    Abstract: A semiconductor device includes a stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Sung Ko, Sung Soon Kim, Wan Sup Shin
  • Patent number: 10325671
    Abstract: A memory system includes: a buffer memory device including a reference voltage pad; a memory controller including a controller ZQ pad; and a controller calibration resistor, wherein the reference voltage pad, the controller ZQ pad, and the controller calibration resistor are coupled to each other.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Hee Jun Kim, Minsoon Hwang
  • Patent number: 10324835
    Abstract: A data storage device includes a first nonvolatile memory device including first LSB, CSB and MSB pages; a second nonvolatile memory device including second LSB, CSB and MSB pages; a data cache memory is configured to store data write-requested from a host device; and a control unit suitable for configuring the first and second LSB pages as an LSB super page, configuring the first and second CSB pages as a CSB super page, and configuring the first and second MSB pages as an MSB super page, wherein the control unit is configured to one-shot programs the data stored in the data cache memory in the first LSB, CSB and MSB pages when determination is made as a data stability mode, and is configured to one-shot programs data stored in the data cache memory in the LSB, CSB and MSB super pages in a performance-improving mode.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Duck Hoi Koo, Yong Jin
  • Patent number: 10326477
    Abstract: Techniques are described for protecting miscorrection in a codeword. In one example, the techniques include obtaining a first set of data to be encoded using a product code comprising one or more constituent codes, and generating a second set of data by performing a miscorrection avoidance procedure on the first set of data. The miscorrection avoidance procedure decreases a probability of miscorrection at a decoder. The techniques further includes jointly encoding the first and the second set of data using an encoding procedure corresponding to the product code to generate at least one encoded codeword, and storing the encoded codeword in the memory.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 18, 2019
    Assignee: SK Hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Yi-Min Lin
  • Patent number: 10324622
    Abstract: A data storage device includes: a plurality of nonvolatile memory devices; and a controller suitable for receiving a command and executing the command for the plurality of nonvolatile memory devices. The controller includes: a first queue suitable for storing the command; and a command manager suitable for managing the command in the first queue, based on a first attribute of the command and queue information of the first queue.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Byung Soo Jung, Dong Yeob Chun
  • Patent number: 10325775
    Abstract: A semiconductor memory device includes a semiconductor layer including a memory cell region; a memory cell array including a plurality of first gate electrode layers stacked over the semiconductor layer, and disposed in the memory cell region; and a capacitor circuit disposed over the semiconductor layer outside the memory cell region. The capacitor circuit includes a plurality of gate structural bodies each including second gate electrode layers stacked over the semiconductor layer, and arranged along a first direction; a plurality of electrodes disposed between the gate structural bodies; and dielectric layers interposed between the gate structural bodies and the electrodes.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang-Hyun Sung, Jeong-Hwan Kim, Jin-Ho Kim
  • Patent number: 10324627
    Abstract: A memory system includes: a nonvolatile memory device suitable for performing a program operation to a page according to an incremental step pulse program scheme, and counting an actual application number of a program pulse for the program operation; and a controller suitable for controlling the nonvolatile memory device to perform the program operation, and reflecting the actual application number to a reference application number of the program pulse for the program operation, which is initially stored in the nonvolatile memory device at a manufacturing phase of the memory system, wherein the nonvolatile memory device determines a failure of the program operation based on a maximum application number of the program pulse for the program operation, which is greater than the reference application number by a predetermined number.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventor: Jiman Hong
  • Patent number: 10326446
    Abstract: A semiconductor apparatus may include a logic circuit, a power gating circuit and a power gating control system. The logic circuit may operate by receiving a first power supply voltage and a second power supply voltage, and may retain an output signal at a predetermined logic value during a standby operation of the semiconductor apparatus. The power gating circuit may apply the first power supply voltage and the second power supply voltage to the logic circuit when a gating control signal is in an enabled state. The power gating control system may test whether the output signal of the logic circuit retains the predetermined logic value when the power gating circuit is turned off, and may generate the gating control signal based on a test result and an operation mode of the semiconductor apparatus.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Bok Rim Ko, A Ram Rim
  • Patent number: 10326473
    Abstract: Techniques for processing bits associated with an “N” multiple level cell NAND flash memory, such as a QLC NAND flash memory, are described. In an example, a system generates a symbol based on the bits. The symbol corresponds to at least two bits. The system encodes the symbol in a non-binary codeword and stores the non-binary codeword in the “N” multiple level cell NAND flash memory based on a mapping between symbols and voltage levels of the “N” multiple level cell NAND flash memory. The system initializes a non-binary decoding procedure based on asymmetric crossover probabilities between the voltage levels. The asymmetric crossover probabilities are defined based on the mapping between the symbols and the voltage level. The system decodes the non-binary codeword based on the non-binary decoding procedure.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 18, 2019
    Assignee: SK Hynix Inc
    Inventors: Aman Bhatia, June Lee, Chenrong Xiong, Naveen Kumar, Fan Zhang, Yu Cai
  • Publication number: 20190179702
    Abstract: An electronic device includes an area control signal generation circuit and an area column control signal generation circuit. The area control signal generation circuit generates an area control signal in response to an operation control signal and an internal information signal. The area control signal includes information on whether each of a plurality of cell areas performs an error correction operation. The area column control signal generation circuit delays a column pulse signal for a delay period, which is determined according to the area control signal, to generate an area column control signal that controls a column operation of the plurality of cell areas.
    Type: Application
    Filed: September 4, 2018
    Publication date: June 13, 2019
    Applicant: SK hynix Inc.
    Inventors: Jae In LEE, Youngjae JIN
  • Publication number: 20190181152
    Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a stack. The semiconductor device may include channel layers including channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern which may be disposed below the stack and couples the channel patterns with the dummy channel patterns. The semiconductor device may include a bit line which is disposed on the stack and coupled with the channel patterns. The semiconductor device may include a well pick-up line which is disposed on the stack and coupled with the dummy channel patterns.
    Type: Application
    Filed: February 14, 2019
    Publication date: June 13, 2019
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI