Abstract: A memory system includes a memory device including a plurality of memory blocks and a controller suitable for controlling the memory device to store a read retry table that includes a plurality of read bias sets respectively corresponding to a plurality of indexes; controlling the memory device to perform a read retry operation with the read bias sets according to an ascending order of the indexes; updating, when a read operation is successfully performed during the read retry operation, the read retry table by including the read levels of the successful read operation into a read bias set of a highest priority index within the read retry table; and controlling the memory device to perform a subsequent read retry operation based on the updated read retry table.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.

Abstract: A MAC operator includes a plurality of multipliers configured to perform a multiplication operation on a floating-point format first data and a floating-point format second data to output a floating-point format multiplication result data, a plurality of floating-point-to-fixed-point converters configured to receive the floating-point format multiplication result data from each of the plurality of multipliers and convert into a fixed-point format multiplication result data to be output, and an adder tree configured to perform an addition operation on the fixed-point format multiplication result data that is output from the plurality of floating-point-to-fixed-point converters. If a first mantissa of the first data and a second mantissa of the second data are composed of ‘M’-bit (‘M’ being a natural number), each of the plurality of multipliers is configured to perform the multiplication operation so that the fixed-point format multiplication result data includes a mantissa of 2*(M+1) bits.

Abstract: An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.

Abstract: An image sensing device includes a pixel array including a plurality of unit pixels coupled to a plurality of row lines, wherein at least one of the unit pixels includes a photo-diode for generating photo charges corresponding to an incident light and a transfer transistor for transferring the photo charges to a floating diffusion (FD) node in response to a transfer control signal transferred through a corresponding row line; a row control circuit disposed at a first side of the pixel array and suitable for providing, to the respective row lines, the transfer control signal having a voltage level between a first voltage and a second voltage; and a bias compensation circuit disposed at a second side of the pixel array and suitable for driving the transfer control signal to the second voltage during a reset read-out section of each of the row lines.

Abstract: A memory system may include: a nonvolatile memory device; and a controller suitable for generating first map information which maps physical addresses of the nonvolatile memory device to logical addresses received from a host, selecting some segments of the first map information as second map information, and outputting the second map information to the host, the controller may determine whether the second map information is updated, and may determine updated map segments as third map information, and the controller may output information to the host indicating the third map information corresponding to a command received from the host.

Abstract: A data processing system is provided to include a memory system to store data and information; and a host in communication with the memory system and including a submission queue for queueing a command to be processed by the memory system, the host configured to provide the memory system with a submission queue tail pointer indicating a tail of the submission queue and command information on a command, wherein the memory system is configured to receive command information on the command, performs a pre-operation on the command based on the command information, and fetches the command from the submission queue based on a result of the pre-operation.

Abstract: A semiconductor device may include: a first electrode; a second electrode; and a multilayer stack that is interposed between the first electrode and the second electrode and includes a seed layer and a high-k dielectric layer, wherein each of the seed layer and the high-k dielectric layer may have a rocksalt crystal structure, and wherein the high-k dielectric layer may exhibit a dielectric constant (k) of fifty (50) or higher.

Abstract: A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

Abstract: A semiconductor device includes an output control circuit configured to generate a pre-output control signal and an output control signal according to the number of times that an output strobe pulse is inputted. The semiconductor device also includes a pipe circuit configured to generate latched data by latching input data on the basis of an input control signal, select some bits of the bits of the latched data and set the selected bits to pre-output data on the basis of the pre-output control signal, and output the pre-output data as output data on the basis of the output control signal.

Abstract: A semiconductor device includes a memory bank including a first memory block, a second memory block, and a redundancy memory block, and a column line selection circuit configured, when a fail occurs in a first column line of the first memory block, to replace the first column line of the first memory block with a first redundancy line of the redundancy memory block, and replace a second column line of the second memory block with a second redundancy line of the redundancy memory block.

Abstract: A memory system includes: a memory device; and a controller suitable for controlling the memory device and including a buffer memory, wherein the controller performs error history logging into the buffer memory in response to a logging start command from a host, stops the error history logging in response to a logging stop command from the host, and provides the host with the logged error history in response to an output command from the host.

Abstract: Techniques related to improving the error floor performance of a bit flipping (BF) decoder are described. In some examples, error floor performance is improved through determining a set of unreliable check nodes (CNs) and using information about the set of unreliable CNs to compute the flipping energies of variable nodes (VNs). In this manner, the flipping energies can be computed more accurately, thereby lowering the error floor. The set of unreliable CNs can be built through applying various criteria, such as criteria relating to the path length to an unsatisfied CN, the degree of a VN in a path to an unsatisfied CN, and/or checksum value. Path length and VN degree can be applied as selection criteria to determine which CNs qualify as members of the set of unreliable CNs. Checksum value can be applied as a trigger condition for building and/or using the set of unreliable CNs.

Abstract: A semiconductor package includes: semiconductor chips being offset-stacked to expose edge regions adjacent to first side surfaces; chip pads disposed in each of the edge regions of the semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to the second chip pad of a semiconductor chip of the semiconductor chips, and another end connected to the first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to the second chip pad of the uppermost semiconductor chip, which is electrically connected to the first chip pad of the uppermost semiconductor chip connected to the horizontal common interconnector.

Abstract: A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k?1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k?1th semiconductor chip when k is 1.

Abstract: A memory system includes a memory device having a plurality of memory blocks for storing data, and a controller configured to perform an erase operation including plural unit erase operations to erase data stored in at least one target memory block included in the plurality of memory blocks. The controller can be configured to perform at least some of the plural unit erase operations onto the at least one target memory block before the at least one target memory block allocated for storing data.

Abstract: A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory access addresses among addresses for memory regions of the memory device; track, for a set period, a number of memory accesses for each memory access address; classify each memory access address into a frequently accessed address or a normal accessed address based on the number of memory accesses in the set period; and allocate the first memory for frequently accessed data associated with the frequently accessed address and the second memory for normal data associated with the normal accessed address.

Abstract: Memory systems, memory controllers, and operation methods of the memory systems are disclosed. In one example aspect, the memory system may suspend a target operation, such as a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. In this way, the memory system may reduce a delay associated with the suspension of program operations and erasure operations.

Abstract: A memory system may include a memory controller suitable for transmitting write data and a first write ECC corresponding to the write data during a write operation, a first error correction circuit suitable for detecting whether the write data received from the memory controller has an error, using the first write ECC received from the memory controller, and correcting the error when the error is detected, a second ECC generation circuit suitable for generating a second write ECC using the write data received from the memory controller, and generating the second write ECC using the write data whose error has been corrected by the first error correction circuit, when the detection of the error is noticed from the first error correction circuit, and one or more memories suitable for storing the second write ECC and write data corresponding to the second write ECC.

Abstract: A memory system includes a memory device, a memory controller configured to control the memory device, and an auxiliary power source configured to supply power to the memory device and the memory controller. The memory controller activates the auxiliary power source in response to the occurrence an NPO (normal power-off) or an SPO (sudden power-off), checks whether there exists an uncompleted operation at a point of time at which the auxiliary power source is activated, and completes the uncompleted operation, and when an amount of residual energy of the auxiliary power source after completing the uncompleted operation exceeds a predetermined threshold value, performs a data verify operation for a predetermined area in the memory device and stores a result of the data verify operation in the memory device.