Abstract: A semiconductor device includes gate structures including conductive layers extending in a first direction; channel structures located in the gate structures and protruding from surfaces of the gate structures; a slit structure located between the gate structures and including a protrusion that protrudes from the surfaces of the gate structures; and a compressive stressor connected to the protrusion of the slit structure and extending in the first direction.

Abstract: A memory device includes adjacent first and second memory blocks, divided by a slit, in which a cell region and a connection region are divided in a direction perpendicular to the adjacent direction. The slit has a first width between the cell region of the first memory block and the cell region of the second memory block, has the first width between the connection region of the first memory block and the connection region of the second memory block, and has a second width wider than the first width in a region where the cell region and the connection region of the first memory block are adjacent to each other and the cell region and the connection region of the second memory block are adjacent to each other.

Abstract: A first impedance calibration part configured to perform a first impedance calibration operation of generating a first impedance calibration code set for adjusting an impedance of a first terminating resistor to a first target value, with reference to an external resistor having a first resistance value. A second impedance calibration part configured to perform a second impedance calibration operation of generating a second impedance calibration code set for adjusting an impedance of a second terminating resistor to a second target value, with reference to a reference resistance unit, a resistance value of which is set to a second resistance value according to a part of the first impedance calibration code set.

Abstract: A memory device includes memory cells connected to a selected word line; a peripheral circuit configured to perform a first program operation of programming a threshold voltage of each of memory cells to a pre-threshold voltage less than a target threshold voltage, and perform a second program operation of programming the threshold voltage of each of the memory cells to the target threshold voltage after the first program operation is performed; and control logic configured to control the peripheral circuit so that a first pass voltage and a second pass voltage are sequentially applied to adjacent word lines, when a program voltage is applied to the selected word line, in the first program operation and the second program operation. A magnitude of the second pass voltage in the first program operation may be greater than a magnitude of the second pass voltage in the second program operation.

Abstract: A memory system may include: a memory device including a plurality of memory blocks; and a memory controller configured to receive a write request including a logical address from an outside, to store write data corresponding to the write request in a first memory block among the plurality of memory blocks, wherein when a map information update is required and the write request is a sequential write operation, to store, in a second memory block, offset information related to a page of the first memory block in which the write data is lastly stored.

Abstract: A color matching circuit of an image sensor includes a receiving end configured to receive an analog pixel signal. The color matching circuit also includes a path controller including a first switch set configured to control current paths between a common node coupled to the receiving end and power sources and a second switch set configured to control signal paths between the common node and analog-to-digital converters, the path controller being configured to determine on-off states of switches included in the first switch set and the second switch set based on a color corresponding to the analog pixel signal. The path controller transfers the analog pixel signal to a target analog-to-digital converter determined depending on the on-off states of the switches, among the analog-to-digital converters.

Abstract: A floating-point data operation circuit configured to perform an addition operation on first input data and second input data in floating-point format. The floating-point data operation circuit includes an exponent processing circuit configured to generate a number of first shift bits for first mantissa data of the first input data and a number of second shift bits for second mantissa data of the second input data using first exponent data of the first input data and second exponent data of the second input data. The exponent processing circuit includes an exponent subtraction circuit configured to generate and output exponent subtraction data by a subtraction operation and to generate and output a 2's complement of the exponent subtraction data, and a first selection output circuit configured to output first shift data and second shift data based on the most significant bit MSB value of the exponent subtraction data.

Abstract: A memory device, and an operating method of the memory device, includes a plurality of memory cells connected between word lines and bit lines and a voltage generator for generating a program voltage or a pass voltage, which is applied to the word lines. The memory device also includes a page buffer group for applying program allow voltages or a program inhibit voltage to the bit lines and a control circuit for controlling the voltage generator and the page buffer group in response to a command. In a program operation of selected memory cells connected to a selected word line among the word lines, the control circuit controls the page buffer group such that the program allow voltages are increased stepwise according to a number of program loops performed on the selected memory cells.

Abstract: A processing-in-memory (PIM) device includes a processing-in-memory (PIM) device includes a memory bank including a left memory bank and a right memory bank, a first global buffer, a second global buffer, a left multiplying-and-accumulating (MAC) operator configured to perform a MAC operation on a first set of a plurality of weight data and a first set of a plurality of vector data, a right MAC operator configured to perform the MAC operation on a second set of the plurality of the weight data and a second set of the plurality of the vector data, and a bias data converter configured to receive bias input data and output bias output data, wherein the bias output data includes a range of numbers that is increased over a range of numbers of the bias input data and includes a value equal to half the value of the bias input data.

Abstract: Provided herein may be an image sensor and a signal conversion method. A signal transducer for converting an analog pixel signal into a digital signal may include an operational amplifier configured to receive a pixel signal, a conversion gain of which is changed, through a first input terminal, receive a ramp signal through a second input terminal, and change polarities of the first input terminal and the second input terminal based on an inverse signal, and a signal manager configured to generate the inverse signal in response to a change in the conversion gain and transfer the inverse signal to the operational amplifier.

Abstract: A processing-in-memory (PIM) system includes a host including an identification (ID)-channel mapper configured to generate a channel address corresponding to an identification received from outside the PIM system, and a plurality of PIM controllers coupled to the host through a plurality of channels, and the plurality of PIM devices coupled to the plurality of PIM controllers through the plurality of channels.

Abstract: Provided is an image processing system and a disparity calculation method. An image processing device included in the image processing system includes a preprocessor configured to determine an effective range of a focal length of an image sensor based on first disparities measured at a plurality of focal lengths of an object having a fixed position from the image sensor, and determine a representative value of equivalent aperture values for the image sensor corresponding to the effective range based on the first disparities. The image processing device also includes a disparity calculator configured to calculate a second disparity of the target object within the effective range based on the focal length, a first distance, a second distance, and the representative value of the equivalent aperture values.

Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.

Abstract: Embodiments of the present disclosure relate to a memory system and operation method thereof. According to embodiments of the present disclosure, the memory system may include i) a memory device including a plurality of memory blocks, wherein each of the plurality of memory blocks include a plurality of pages; and ii) a memory controller configured to determine a first super memory block among a plurality of super memory blocks, wherein each of the plurality of super memory blocks includes one or more of the plurality of memory blocks, set a lock to prevent a background operation from being executed for the first super memory block, and transmit data stored in the first super memory block to an external device.

Abstract: A semiconductor device includes a substrate, a bit line conductive layer disposed on the substrate and extending in a first lateral direction substantially parallel to a surface of the substrate, first and second channel structures disposed on the bit line conductive layer to be spaced apart from each other in the first lateral direction, first and second gate dielectric layers disposed on side surfaces of the first and second channel structures over the substrate, first and second gate line conductive layers disposed on the first and second gate dielectric layers, respectively, the first and second gate line conductive layers common to the first and second channel structures, respectively, and extending in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate, and first and second storage node electrode layers disposed over the first and second channel structures, respectively.

Abstract: A machine learning device including a general-purpose memory module interface is disclosed. The machine learning device includes a data storage circuit configured to store raw data and command data received from a host device through a memory module interface, and store machine learning data as a result of machine learning of the raw data and location data of the machine learning data, a machine learning logic circuit configured to generate the machine learning data through the machine learning of the raw data according to a pre-programmed machine learning logic, and a machine learning controller configured to read the raw data from the data storage circuit based on the command data, transmit the read raw data to the machine learning logic circuit, and write the machine learning data and the location data in the data storage circuit.

Abstract: A semiconductor apparatus may include a repair circuit configured to activate a redundant line of a cell array region by comparing repair information and address information. The semiconductor apparatus may include a main decoder configured to perform a normal access to the cell array region by decoding the address information. The address information may include both column information and row information.

Abstract: The present technology includes a method of operating a controller that controls a semiconductor memory device including a plurality of memory blocks. The method includes receiving a read request for data included in any one memory block among the plurality of memory blocks from a host, and controlling the semiconductor memory device to read data corresponding to the read request using a read-history table. The read-history table includes read voltages used for a plurality of read pass operations for the any one memory block, respectively.

Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

Abstract: The present technology relates to a memory controller and a method of operating the same. The memory controller may include a block manager designating a first memory block as an open block, which is driven to program m-bit data per cell, where m is a natural number, an address manager increasing an access count value corresponding to a logical address for the first memory block whenever a program request or a read request including the logical address is received from a host, and a data manager determining a representative attribute of data programmed in the first memory block based on access count values for the logical addresses for the first memory block when a flush request is received from the host. The block manager may determine whether to designate a new open block according to the determined representative attribute.