Patents Assigned to SK Hynix Inc.
  • Publication number: 20200220537
    Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Applicant: SK hynix Inc.
    Inventor: Kyu Dong HWANG
  • Publication number: 20200220536
    Abstract: A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.
    Type: Application
    Filed: March 23, 2020
    Publication date: July 9, 2020
    Applicant: SK hynix Inc.
    Inventor: Seung Ho LEE
  • Publication number: 20200218671
    Abstract: A semiconductor device, semiconductor system, and system may be provided. The semiconductor system may include one semiconductor device of a first semiconductor device and a second semiconductor device suitable for transmitting and receiving addresses and encrypted data. The one semiconductor device may include an address output circuit configured to output the addresses. The one semiconductor device may include an encryption circuit configured to output the encrypted data based on normal data and the addresses. The one semiconductor device may include a decryption circuit configured to output the normal data based on the addresses and the encrypted data.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Applicant: SK hynix Inc.
    Inventor: Yong-Deok CHO
  • Publication number: 20200219583
    Abstract: A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Applicant: SK hynix Inc.
    Inventors: Woongrae KIM, Bok Rim KO, Keun Soo SONG
  • Publication number: 20200219582
    Abstract: An integrated circuit chip includes a first through electrode and a second through electrode formed through the integrated circuit chip, a transmission circuit suitable for selecting one of signals transmitted through the first and second through electrodes, respectively, and transmitting the selected signal to a data line, in response to a selection signal, and a selection signal generation circuit suitable for generating the selection signal by toggling the selection signal, during a test operation.
    Type: Application
    Filed: October 29, 2019
    Publication date: July 9, 2020
    Applicant: SK hynix Inc.
    Inventors: Ji-Hwan KIM, Sang-Muk OH
  • Publication number: 20200219584
    Abstract: A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Applicant: SK hynix Inc.
    Inventors: Woongrae KIM, Bok Rim KO, Keun Soo SONG
  • Publication number: 20200219546
    Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal and a command/address signal. The controller includes a controller termination circuit turned on during a read operation. The controller receives first data through an input/output (I/O) line coupled to the controller termination circuit during the read operation and outputs second data through the I/O line coupled to the controller termination circuit turned off during a write operation. The semiconductor device includes an internal termination circuit turned off during the read operation, outputs the first data through the I/O line coupled to the internal termination circuit based on the chip selection signal and the command/address signal during the read operation, and stores the second data inputted through the I/O line coupled to the internal termination circuit turned on during the write operation.
    Type: Application
    Filed: August 7, 2019
    Publication date: July 9, 2020
    Applicant: SK hynix Inc.
    Inventors: Yoo Jong LEE, Kang Sub KWAK, Young Jun YOON
  • Patent number: 10706939
    Abstract: Provided herein may be a memory device, a memory system, and a method of operating the memory device. When all of normal operation loops associated with a program operation or an erase operation of a memory cell fail, a retry operation of repeating at least one of the normal operation loops is performed in consideration of the degraded state of at least one of a source select transistor, a drain select transistor, and a dummy cell.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Jong Wook Kim
  • Patent number: 10705746
    Abstract: A memory system includes: a controller for selecting a pre-coding mode or a normal write mode in response to a host interface mode change command inputted from a host device; and a semiconductor memory device for storing, in an operating system (OS) storage area, OS data inputted from the host device in the pre-coding mode under the control of the controller.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Kwang Su Kim
  • Patent number: 10707861
    Abstract: A semiconductor apparatus may include a logic circuit and a power gating circuit including a gating transistor configured to apply a first supply voltage to the logic circuit based on an operation mode of the semiconductor apparatus. The semiconductor apparatus may be configured to monitor a characteristic of the logic circuit and adjust aback bias voltage to the gating transistor based on the characteristic of the logic circuit.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10707899
    Abstract: Techniques are described for performing a bit-flipping decoding scheme on a G-LDPC codeword. In an example, a decoding system uses two syndrome tables. The first syndrome table identifies a predefined syndrome for a component codeword that protects a bit of the G-LDPC codeword. This predefined syndrome is identified based on a location of the bit and is used to update a current syndrome of the component codeword. The second syndrome table identifies one or more bit error locations for the component codeword. The bit error locations are identified from the second syndrome table based on the current syndrome of the component codeword, as updated. In an example, the error locations are used to update a reliability of the bit if its location corresponds to one of the error locations. A bit flipping decision is made for the bit based on its reliability.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 7, 2020
    Assignee: SK Hynix Inc.
    Inventors: Aman Bhatia, Naveen Kumar, Chenrong Xiong, Fan Zhang, Xuanxuan Lu, Yu Cai
  • Patent number: 10706899
    Abstract: A semiconductor device includes a buffer control circuit suitable for generating a buffer control signal in response to a power-down mode signal and a detection pulse, a first buffer circuit suitable for generating a first internal chip select signal by buffering a chip select signal depending on a select signal which is generated in response to the buffer control signal in a power-down mode, and a detection pulse generation circuit suitable for generating the detection pulse in response to the first internal chip select signal.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Sangkwon Lee
  • Patent number: 10708011
    Abstract: An apparatus for determining an eye mask of a device under test (DUT) which is configured to receive a data bit stream signal including a threshold level value and output a data bit stream output signal. The apparatus includes an input unit configured to receive the data bit stream output signal provided by the DUT, an evaluation unit configured to evaluate the received data bit output signal and provide an evaluation result, and a controller configured to change the threshold level value in response to the evaluation result. The apparatus is integrated into the DUT and can operates autonomously without multiple interactions with a tester.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 7, 2020
    Assignee: SK Hynix Inc.
    Inventors: Jinliang Mao, Chee Hoe Chu
  • Patent number: 10706933
    Abstract: A semiconductor device includes a mode setting circuit configured to allocate any one of values to a mode signal based on an event signal, an address converter configured to generate a conversion address by converting at least one address based on the mode signal, and a memory circuit configured to perform an operation corresponding to the conversion address.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Jin Byun
  • Patent number: 10706898
    Abstract: A semiconductor apparatus may include: a pad unit including a plurality of pads; a memory cell array coupled to the pad unit through input/output signal lines; and a pad configuration control circuit configured to change a pad configuration of the pad unit by dividing the plurality of pads into a plurality of groups and setting the plurality of groups to different modes, respectively.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Myoung Seo Kim, Seung Yong Lee, Young Pyo Joo
  • Patent number: 10706908
    Abstract: A semiconductor memory device includes: first to Nth memory banks each including a normal cell region coupled to normal word lines and a redundant cell region coupled to redundant word lines; first to Nth non-volatile memories that correspond to the first to Nth memory banks, respectively, each including a plurality of memory sets for programming repair addresses of the corresponding memory banks; a refresh control circuit for generating first to Nth count values by counting a number of the memory sets used in the first to Nth non-volatile memories, and generating a redundant reset signal based on the first to Nth count values; and an address generation circuit for sequentially generating normal addresses for selecting the normal word lines and redundant addresses for selecting the redundant word lines based on a refresh signal, and initializing the redundant addresses based on the redundant reset signal.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Do-Hong Kim
  • Patent number: 10706927
    Abstract: An operating method of an electronic device including a semiconductor memory, the operating method includes selecting one of a plurality of memory cells during a set operation, applying a write current having a slow quenching pattern to the selected memory cell, monitoring a cell current flowing through the selected memory cell, generating a discharge control signal corresponding to a result of the monitoring, and discharging the write current in response to the discharge control signal.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Seok-Man Hong, Tae-Hoon Kim
  • Patent number: 10705757
    Abstract: There are provided a memory interface, a command queue controller configured to determine an execution order of normal commands and a suspend command; a command time controller configured to receive the normal commands, and output command and time information by providing a corresponding additional operation time to each of the normal commands; a command time manager configured to match the command and time information to each of the normal commands to be stored therein, and output an end signal; and an input/output interface configured to receive the normal commands and the suspend command, and transmit the normal commands and the suspend command to a memory device through a channel.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung Kwan Hong, Ik Sung Oh
  • Patent number: 10706929
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin
  • Patent number: 10706932
    Abstract: A memory device prevents generation of an abnormal column address. The memory device includes: a memory cell array; and a column address controller configured to generate a column address of the memory cell array in response to a column address control signal, wherein the column address controller enables the column address control signal when an address signal is input, and wherein the address signal includes a column address signal corresponding to the column address.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Eun Kyu In, Jae Woo Park, Seok Won Park, Byung Ryul Kim