Patents Assigned to SK Hynix Inc.
  • Patent number: 11062768
    Abstract: A semiconductor memory apparatus may include a memory bank, a global buffer array, and an input and output circuit. The memory bank includes a local data circuit, and the global buffer array includes a global data circuit. The local data circuit is operably coupled to the global data circuit. The global buffer array may be operably coupled to the input and output circuit. The memory bank is disposed in a core region, and the global buffer array and the input and output circuit may be disposed in a peripheral region separated from the core region.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Dong Keun Kim
  • Patent number: 11061615
    Abstract: A memory system, a memory controller and an operating method thereof. The memory system includes a memory device including a plurality of memory blocks; and a memory controller configured to control the memory device. During an idle time, the memory controller searches for a target read bias for a first word line among a plurality of word lines in a first memory block of the memory device, and generates a history including the target read bias.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Hyung-Seok Yu
  • Patent number: 11062783
    Abstract: A memory device includes a memory cell array having a plurality of memory strings and includes a voltage generating circuit configured to generate and apply a plurality of drain select line voltages, a plurality of source select line voltages, and a read voltage to the memory cell array during a read operation. The memory device also includes control logic configured to control the voltage generating circuit to generate a first drain select line voltage applied to a first unselected memory string among unselected memory strings among the plurality of memory strings and a second drain select line voltage applied to second unselected memory strings among the unselected memory strings during the read operation, wherein the second drain select line voltage is different from the first drain select line voltage.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Moon Sik Seo
  • Patent number: 11061616
    Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a target block manager configured to store a target block address on which a refresh operation is to be performed and output a refresh signal for the target block corresponding to the target block address when an auto refresh command is received, and a data transmission controller configured to output a transmission signal and a buffer control signal for transmitting data between the target block or the buffer block and the temporary buffer circuit in response to the refresh signal.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Won Jae Choi, Ki Chang Gwon
  • Patent number: 11061593
    Abstract: A memory system includes a non-volatile memory device including at least one memory blocks storing a data and a controller coupled to the non-volatile memory device. The controller can perform at least one program operation or at least one erase operation within the at least one memory block. The controller can recognize an operation status of the at least one memory block in response to a time consumed for completing the at least one operation, and determine whether the at least one memory block is used and which priority is given to the at least one memory block based at least on the operation status so that the at least one memory block is allocated for a following operation.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11062741
    Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Jun Yoon, Hyun Seung Kim
  • Patent number: 11061607
    Abstract: There are provided an electronic system and an operating method thereof. The electronic system includes: a host for queuing an external command to wait or to be output, based on a status of dies included in a storage device; a central processing unit for generating a command for controlling the storage device in response to a request received from the host or the external command; and a controller memory buffer for storing status information indicating whether the dies are in a status in which access is possible or a status in which access is impossible, wherein the central processing unit receives status information of the dies from the storage device, and stores status information matched to each of the dies in the controller memory buffer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Duck Hoi Koo, Yong Jin
  • Patent number: 11062760
    Abstract: A memory device includes a plurality of data input/output (I/O) groups each including data I/O circuits, each data I/O circuit comprising a transistor having a predetermined threshold voltage according to a bulk voltage supplied to a bulk terminal thereof; a control circuit suitable for generating a control signal according to a data I/O mode; and a plurality of voltage supply circuits suitable for independently supplying bulk voltages to the plurality of data I/O groups, and changing, in response to the control signal, a level of a bulk voltage corresponding to data I/O groups unused in the data I/O mode, among the plurality of data I/O groups.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Insung Koh
  • Patent number: 11062758
    Abstract: Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Yu Cai, Fan Zhang
  • Patent number: 11061614
    Abstract: An electronic apparatus includes a storage device having a plurality of memory blocks including a first memory block; and a controller configured to control the storage device to perform a read operation for the first memory block in response to a read request of a host. The controller controls the storage device to perform a refresh operation for the first memory block based on whether there is a difference value between a current pass read voltage and a previous pass read voltage which were applied to the first memory block when performing the read operation, and whether there is a difference between a current erase/write count and a previous erase/write count for the first memory block.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Chui Sung Kang
  • Patent number: 11062750
    Abstract: A semiconductor device includes a phase control signal generation circuit, a phase detection circuit, and a selection/transmission circuit. The phase control signal generation circuit outputs one of a command-shifted signal generated from a command/address signal and a clock-shifted signal generated from a clock signal as a phase control signal, based on a leveling enablement signal. The phase detection circuit detects a phase of a leveling clock signal in synchronization with the phase control signal to generate a detection signal. The selection/transmission circuit outputs the detection signal as one of a phase detection signal and a phase adjustment signal based on the leveling enablement signal.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Yoo Jong Lee, Kang Sub Kwak
  • Patent number: 11062749
    Abstract: A semiconductor device includes a read control circuit configured to generate first and second output control signals including pulses which are selectively generated, from first and second strobe signals depending on burst information; and a data output circuit configured to latch first internal data depending on the pulse of the first output control signal, transfer second internal data at a time when the second output control signal level-transitions, and generate output data from the latched first internal data and the transferred second internal data.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Kwang Hun Lee, Sang Sic Yoon
  • Patent number: 11062769
    Abstract: A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Dong Keun Kim
  • Publication number: 20210209022
    Abstract: A PIM device includes a plurality of first storage regions, a second storage region, and a column control circuit. The second storage region is coupled to each of the plurality of first storage regions through a data transmission line. The column control circuit generates a memory read control signal for reading data stored in an initially selected storage region of the plurality of first storage regions and a buffer write control signal for writing the data read from the initially selected storage region to the second storage region. The column control circuit generates a global buffer read control signal for reading the data written to the second storage region and a memory write control signal for writing the data read from the second storage region to a subsequently selected storage region of the plurality of first storage regions.
    Type: Application
    Filed: December 30, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208884
    Abstract: A MAC operator includes a plurality of data type converters and a plurality of multipliers. Each of the plurality of data type converters may receive 16-bit input data of one of first to fourth data types of a floating-point format to convert into L-bit output data of the floating-point format. Each of the plurality of multipliers may perform a multiplication on the “L”-bit output data of the floating-point format outputted from two of the plurality of data type converters to output multiplication result data of the floating-point format.
    Type: Application
    Filed: March 1, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210125
    Abstract: A processing-in-memory (PIM) system includes a host and a PIM controller. The host is configured to generate a request for a memory access operation or a multiplication/accumulation (MAC) operation of a PIM device and also to generate a mode definition signal defining an operation mode of the PIM device. The PIM controller is configured to generate a command corresponding to the request to control the memory access operation or the MAC operation of the PIM device. When the operation mode of the PIM device is inconsistent with a mode set defined by the mode definition signal, the PIM controller controls the memory access operation or the MAC operation of the PIM device after changing the operation mode of the PIM device.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208878
    Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a multiplier for performing a multiplying calculation of the first data and the second data. The arithmetic circuit is configured to perform a multiplication/accumulation (MAC) arithmetic operation of the first data and the second data. The arithmetic circuit includes a zero-detection circuit configured to disable input of the multiplier and to output zero data including multiple bits having a value of ‘0’ as output data of the multiplier, when all bits included in at least one of the first data and the second data have a value of ‘0’.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventors: Mun Gyu SON, Choung Ki SONG
  • Publication number: 20210208881
    Abstract: A neural network system includes a data type converter and a MAC operator. The data type converter may convert 32-bit floating-point format into one of a plurality of 16-bit floating-point formats. The MAC operator may perform MAC operations using 16-bit floating-point format data converted by the data type converter. The MAC operator includes a data type modulator configured to modulate the bit number of the converted 16-bit floating-point format to provide a modulated floating-point format with bit number different from the bit number of the converted 16-bit floating-point format.
    Type: Application
    Filed: February 12, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208894
    Abstract: A PIM device writes elements of a first matrix to a first memory bank, and may writes elements of a second matrix to a second memory bank. The PIM device simultaneously reads elements with the same order among the elements of the first and second matrices by simultaneously accessing the first and second memory banks. An MAC operator generates arithmetic data by performing a calculation on data that is read from the first and second memory banks, and writes the arithmetic data to a third memory bank.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210551
    Abstract: A resistive memory device includes a vertical word line pillar, a plurality of resistive layers, a gate insulation layer, and a channel layer. The vertical word line pillar is formed on a semiconductor substrate. The resistive layers are stacked at both sides of the vertical word line pillar. The gate insulation layer is interposed between the vertical word line pillar and the resistive layers. The channel layer is arranged between the gate insulation layer and the resistive layers.
    Type: Application
    Filed: June 29, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Jae Hyun Han