Abstract: Disclosed are a controller and an operating method thereof. According to an embodiment of the present disclosure, a controller that controls a memory device, comprises: a host interface for determining a remaining resource index and outputting a task scheduling instruction when a data throughput determined based on data inputted/outputted between a host and the controller is lower than a maximum throughput required under a current workload pattern; and a processor for: selecting, in response to the task scheduling instruction, at least one of a plurality of internal tasks based on the remaining resource index and resource consumption indexes of the respective internal tasks, and performing the selected internal task while performing an input/output task.

Abstract: A storage device includes a memory device including a plurality of memory blocks, and a controller configured to move first data from a single level cell (SLC) memory block to a first memory block having a target density lower than a maximum density based on a waiting time and to move second data from the SLC memory block to a memory block having the maximum density based on the waiting time.

Abstract: A semiconductor device includes a first redistribution layer pattern, a second redistribution layer pattern, and a recognition mark. The first redistribution layer pattern is formed on a semiconductor substrate. The second redistribution layer pattern, with a bonding pad portion, is disposed on the first redistribution layer pattern. Furthermore, the recognition mark is formed on the first redistribution layer pattern to indicate a position of the bonding pad portion.

Abstract: Disclosed are a capacitor for DRAM, a DRAM including the same, and a method of fabricating the same. The DRAM capacitor according to an embodiment may include a first electrode of the DRAM; a second electrode spaced apart from the first electrode; and a dielectric layer including a HfZrO film disposed between the first electrode and the second electrode. The HfZrO film may have an intermediate state corresponding to a phase transition region between a first state in which a tetragonal crystalline phase with anti-ferroelectricity property or a tetragonal crystalline phase is dominant, and a second state in which the orthorhombic crystalline phase with anti-ferroelectricity property or the orthorhombic crystalline phase is dominant. The HfZrO film may include both of the tetragonal crystalline phase and the orthorhombic crystalline phase. The HfZrO film maintains an intermediate state corresponding to the phase transition region within the operating voltage range of the capacitor.

Abstract: Disclosed is an image sensor including a pixel array, wherein the pixel array includes a first sub-pixel array including pixels disposed in a first diagonal direction and each having a green filter, and pixels disposed in a second diagonal direction and each having a yellow filter; a second sub-pixel array including pixels disposed in the first diagonal direction and each having the green filter, and pixels disposed in the second diagonal direction and each having the yellow filter; a third sub-pixel array including pixels disposed in the second diagonal direction and each having a red filter, and pixels disposed in the first diagonal direction and each having a magenta filter; and a fourth sub-pixel array including pixels disposed in the second diagonal direction and each having a blue filter, and pixels disposed in the first diagonal direction and each having a cyan filter.

Abstract: An error handling device includes a cross-voltage sense amplifier and an error handling circuit. The cross-voltage sense amplifier is configured to perform a normal sense operation and a cross sense operation. The normal sense operation generates normal sense data by providing an input voltage and a comparison voltage to first and second inputs of a comparator, respectively. The cross sense operation generates cross sense data by providing the input voltage and the comparison voltage to the second and first inputs of the comparator, respectively. The error handling circuit identifies a location of an error using the normal sense data and the cross sense data and corrects the error.

Abstract: Disclosed is an image sensing system including a first sub-pixel array having an arrangement of K×K pixels, where “K” is a natural number greater than 4, wherein the first sub-pixel array includes: first pixels disposed in a first diagonal direction and each having a green filter; second pixels disposed in a second diagonal direction that intersects the first diagonal direction and each having a red filter, and third pixels disposed in the second diagonal direction and each having a blue filter; and fourth pixels each having a white filter and disposed at the other positions except for arrangement positions of the first to third pixels disposed in the first and second diagonal directions, and fifth pixels suitable for measuring depth information, and the fourth pixels and the fifth pixels are disposed in a first pattern.

Abstract: A pooled memory device includes plural memory devices and a controller. The plural memory devices include a first memory and a second memory with at least one power supply configured to control power supplied to each of the plural memory devices. The controller is coupled to an interconnect device which is configured to provide the plural memory devices to at least one external device as a logical device. The controller is configured to track available storage capacities of the first memory and the second memory and cut off power supplied to an unused memory among the first memory and the second memory.

Abstract: A memory device, and a method of manufacturing the same, includes a gate stack formed on a cell region and a pass transistor region, a plurality of cell plugs extending in a vertical direction in the gate stack of the cell region, a plurality of gate contact structures extending in the vertical direction by passing through the gate stack of the pass transistor region, and a plurality of pass transistors connected to the plurality of respective gate contact structures. Each of the plurality of pass transistors has a cylindrical shape structure.

Abstract: An electronic device includes an internal voltage generation circuit configured to detect a voltage level of an internal voltage, that is generated by the internal voltage generation circuit. The internal voltage generating circuit is also configured to generate a drive code, which, along with a drive clock, determines the magnitude of the generated internal voltage. The drive code may be reset responsive to the internal voltage. The electronic device also includes a load circuit which is powered by the generated internal voltage.

Abstract: A semiconductor system includes a controller configured to output a command and address for performing an ECS operation after the start of entry into a power-down operation, receive data and output the data in response to correcting one or more errors occurring in the data, and output a command for performing a self-refresh operation when the ECS operation is terminated, and a semiconductor device configured to output, as the data, internal data stored in multiple memory cells after the start of a read operation of the ECS operation in response to receiving the command and address, receive the data having the one or more errors corrected after the start of a write operation of the ECS operation, store the data having the one or more errors corrected, and perform a self-refresh operation on the multiple memory cells after receiving the command when the ECS operation is terminated.

Abstract: A receiver circuit includes a first buffer, a second buffer, and a sampling circuit. The first buffer receives a multi-level signal according to a first reference voltage to generate a first input signal. The second buffer receives the multi-level signal according to a second reference voltage to generate a second input signal. The sampling circuit samples each of the first input signal and the second input signal according to a first equalization method and a second equalization method, respectively, and outputs at least one of a first sampling result value according to the first equalization method and a second sampling result value according to the second equalization method according to a logic value of a previously input multi-level signal.

Abstract: A receiver circuit is configured to generate a reception symbol from a multi-level signal. The receiver circuit is configured to generate three compensation signal pairs from an input signal pair to perform a loop unrolled decision feedback equalization operation. A first summing circuit is configured to equalize the input signal pair with a first offset to generate a first compensation signal pair, and a second summing circuit is configured to equalize the input signal pair with a second offset to generate a second compensation signal pair. An averaging circuit is configured to average the first compensation signal pair and the second compensation signal pair to generate a third compensation signal pair.

Abstract: A memory device, and a method of manufacturing the same, includes a discharge contact, a source pattern surrounding a periphery of the discharge contact and floated, and a source line surrounding a periphery of the source pattern and to which a source voltage is applied. The memory device also includes a separation pattern electrically isolating the source pattern and the source line, main support patterns positioned on the source pattern, sub support patterns positioned on the source line, and a contact positioned on the discharge contact.

Abstract: Provided herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array including a plurality of memory cells coupled to a selected word line, a voltage generator configured to generate an operating voltage that is used for an internal operation, a row decoder configured to perform an under-drive operation including decreasing a voltage level of the selected word line and to apply the operating voltage to the selected word line, and control logic configured to control the row decoder to apply a ground voltage to the selected word line during the under-drive operation.

Abstract: An electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.

Abstract: A memory system includes: a storage device for storing data; a system memory in which normal firmware and debugging firmware are stored; a firmware implementer for implementing the normal firmware or the debugging firmware; and a controller for controlling the storage device in a normal mode in which the memory system is driven by the normal firmware. When an error detected in the normal mode is uncorrectable, the controller uploads the debugging firmware stored in the system memory to the firmware implementer to change the normal mode to a debugging mode. The firmware implementer performs a debugging operation on the storage device by implementing the uploaded debugging firmware.

Abstract: A controller includes at least one register configured to store a doorbell regarding a submission queue storing at least one request generated by a host, a first cache configured to store data corresponding to a first result of an operation performed in response to the at least one request, a second cache configured to store data corresponding to a second result of an operation performed in response to a read look ahead (RLA) request generated based on the at least one request, and a cache size manager configured to adjust a size of the second cache based on an update cycle of the doorbell and a change of a number of the at least one request corresponding to the doorbell.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.

Abstract: A semiconductor device includes a selection input circuit and a core data generation circuit. The selection input circuit is configured to generate selection data, a selection parity, and a selection data control signal from data, a parity, and a data control signal during a write operation and sets the selection data, the selection parity, and the selection data control signal to a predetermined logic level during a pattern write operation. The core data generation circuit is configured to receive drive data, a drive parity, and a drive data control signal driven by the selection data, the selection parity, and the selection data control signal to generate core data which are stored into a memory core according to whether an error correction operation and a data inversion operation is performed.