Abstract: A semiconductor memory device and a method for fabricating the same are provided. The semiconductor memory device includes a plurality of gate stacks separated by a plurality of slit structures, and each of the gate stacks includes: a first stack including three or more first conductive patterns spaced apart from one another at substantially a same level; a second stack formed on the first stack and including second conductive patterns and interlayer dielectric layers alternately stacked; and a plurality of channel structures penetrating the second stack and the first stack.

Abstract: The present disclosure relates to a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a gate stacked structure, a channel layer passing through the gate stacked structure in a vertical direction, a memory layer disposed between the channel layer and the gate stacked structure, a dummy stacked structure extended toward the gate stacked structure, a first dummy pattern passing through the dummy stacked structure in the vertical direction, and a gap arranged in the first dummy pattern.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on a substrate; a plurality of channel structures penetrating the gate stack structure, each of the plurality of channel structures with one end portion protruding past a boundary of the gate stack structure; and a source layer formed on the gate stack structure. The protruding end portion of each of the plurality of channel structures extends into the source layer. The protruding end portion of each of the plurality of channel structures has a flat section.

Abstract: With regard to a function group including all or some functions included in one of multiple binary codes stored in the memory device, a binary code including a first function that is executed at a first timepoint is loaded into a first memory area at a second timepoint that precedes the first time point, thereby minimizing the operation delay time of the memory system, and minimizing the overhead occurring in the processing of calling a specific function.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may receive, from an outside of the memory system, a read command, execute a defense code on the data when a failure occurs during an operation of reading data from the memory device in response to the read command, and transmit defense code information, which is information related to the execution of the defense code for data, to the outside of the memory system.

Abstract: An image sensing device includes a first unit pixel block, a second unit pixel block, and an isolation transistor. The first unit pixel block includes a first common floating diffusion node, first photoelectric conversion elements, first transfer transistors and a first conversion gain transistor configured to change capacitance of the first common floating diffusion node. The second unit pixel block adjacent to the first unit pixel block includes a second common floating diffusion node, second photoelectric conversion elements, second transfer transistors and a second conversion gain transistor configured to change capacitance of the second common floating diffusion node. The isolation transistor located in a boundary region between the first unit pixel block and the second unit pixel block isolates the first conversion gain transistor and the second conversion gain transistor from each other.

Abstract: A substrate includes: a first die alignment mark and a first die position mark defining a die stack region. The first die alignment mark has substantially a cross shape having substantially a vertical bar and substantially a horizontal bar intersecting each other substantially perpendicularly, and the first die position mark includes a first main position mark having a first area and a first branch position mark having a second area different from the first area.

Abstract: The present technology may include: a current mirror configured to apply a test current that is generated by a test voltage to a selected word line, among a plurality of word lines, and to generate a copy current by copying the test current; a comparison circuit configured to compare at least one reference current with the copy current to generate a comparison result signal; and a test control circuit configured to perform a first noise control mode that charges unselected word lines, among the plurality of word lines, with electric charges, in response to a test mode signal and floats the unselected word lines.

Abstract: Electronic device and operation method for an electronic device are provided. In the electronic device, a specific number of protocol data units (PDUs) are received as a PDU block to be transmitted. The PDU block includes at least one PDU belonging to a control PDU category. A control block is generated according to the PDU block by reordering, wherein the control block includes a header being placed before all PDUs of the PDU block and indicating a control block category; in the control block, any PDU belonging to the control PDU category in the PDU block is placed after the header and before any PDU belonging to a data PDU category in the PDU block. The control block is transmitted through the electronic device to another electronic device according to an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding.

Abstract: A shift array circuit generates output data having the number of bits greater than the number of bits of target data by shifting the target data by a bit corresponding to a value of shift data. The shift array circuit includes a plurality of shift arrays. The plurality of shift arrays is configured to receive bits of the shift data for each bit and each configured to perform a shift operation on input data that is input to each of the plurality of shift arrays by a shift bit corresponding to an input bit, among the bits of the shift data.

Abstract: An image sensor includes: a unit pixel configured to output pixel data in response to a drive signal being input to the unit pixel; and a control circuit configured to provide the unit pixel with a first drive signal and a second drive signal each having a first phase, and a third drive signal having a second phase with a phase difference of 180 degrees with respect to the first phase in a first mode, the control circuit providing the unit pixel with the first drive signal having the first phase, the second drive signal having the second phase, and the third drive signal having a deactivation voltage in a second mode.

Abstract: System, method for circuit validation, and system and method for facilitating circuit validation are provided. The circuit validation system comprises a prototype system and a computing device. The prototype system comprises a programming logic device circuit configured to implement a modified circuit design. The modified circuit design includes a circuit module as a design under test (DUT), an input generation circuit coupled to the circuit module for outputting input signals to the circuit module in response to a test signal, and an output acquisition circuit coupled to the circuit module for storing output data from the circuit module. The computing device is capable of being coupled to the prototype system and configured to generate the test signal to perform a test of the DUT on the prototype system.

Abstract: Method for control protocol frame transmission and electronic device are provided. The method comprises following operations. By the electronic device operating in an advanced line encoding mode and having a first burst from the electronic device to the other electronic device, the first burst is closed and a second burst is opened from the electronic device to the other electronic device for request frame transmission, wherein the electronic device operating in the advanced line encoding mode is configured to transmit data by using an advanced line encoding having an effective data rate larger than an effective data rate of 8b/10b encoding. By the electronic device, a request frame is transmitted in the second burst.

Abstract: A stack package includes a first die stack including first dies, a second die stack including second dies, and an insert die between the first die stack and the second die stack, wherein the insert die is thicker than each of the first and second dies.

Abstract: A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes a memory block including a plurality of sub-blocks, a peripheral circuit configured to perform a program operation on the memory block, and control logic configured to control the peripheral circuit to perform the program operation on the memory block, wherein the program operation comprises programming to program normal data to a first sub-block, allocated to be a normal sub-block, among the plurality of sub-blocks, and programming parity data of the normal data to a second sub-block, allocated to be a backup block, among the plurality of sub-blocks.

Abstract: Method for facilitating testing for an interconnection protocol, a controller, and an electronic device are provided. The method is suitable for an electronic device capable of communicating with another electronic device. The method comprises the following steps. At a controller of the electronic device, a test mode request signal is received to enter a test mode in which data transmission is to be performed by using an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding. At the controller, a test data signal is generated to indicate a test pattern including an ordered set portion and a data pattern portion by using the advanced line encoding. The test data signal is transmitted according to the advanced line encoding through the electronic device to the other electronic device.

Abstract: A test device may include a test memory device, an insulation layer and a charge injection electrode. The test memory device may include a memory layer and a gate electrode layer on a semiconductor substrate. The insulation layer may be arranged on the test memory device. The charge injection electrode may be arranged on the insulation layer to inject a charge into the test memory device based on a voltage.

Abstract: A method for facilitating frame error handling and an electronic device are provided. The method is for use in an electronic device capable of communicating with another electronic device. The method comprises the following. In response to an error event in an advanced line encoding mode, closing a first burst transmission and opening a second burst transmission are performed, wherein the advanced line encoding mode indicates that the electronic device is capable of data transmission by using an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding. A lane alignment pattern is transmitted in the advanced line encoding mode from the electronic device to the other electronic device after the second burst transmission is opened. A negative acknowledgement control frame is transmitted in the advanced line encoding mode from the electronic device to the other electronic device after the lane alignment pattern is transmitted.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.

Abstract: A sensing and amplifying circuit includes a driving voltage control circuit configured to control a voltage level of a driving voltage based on a surrounding temperature of the sensing and amplifying circuit, a delay control circuit configured to generate a line connection signal and an inverted line connection signal in response to a delay start signal by being supplied with the driving voltage, and a sense amplifier configured to perform a sensing and amplifying operation in response to the line connection signal and the inverted line connection signal. An interval between enable timing of the line connection signal and enable timing of the inverted line connection signal is adjusted as the surrounding temperature changes.