Abstract: A method of forming patterns includes: forming a hard mask layer on a target layer, coating a cleavage relief layer on the hard mask layer to fill cleavages generated in the hard mask layer, forming photoresist patterns on the cleavage relief layer, removing portions of the cleavage relief layer and portions of the hard mask layer using the photoresist patterns as a first etch mask to form hard mask patterns, removing portions of the target layer using the hard mask patterns as a second etch mask to form target layer patterns, and removing the hard mask patterns. The hard mask layer includes an amorphous carbon layer (ACL), and the cleavage relief layer includes a spin-on carbon (SOC) layer.

Abstract: A storage device may receive, from an external device, a target read recovery level indicating information on a read command execution completion time and an error recovery amount requested by the external device, may read, from a memory, data requested by a read command transmitted by the external device, and may transmit, to the external device, a response regarding a result of executing the read command transmitted by the external device within the read command execution completion time indicated by the target read recovery level.

Abstract: A memory device includes a memory cell array including a first memory cell connected to a first channel structure, and a second memory cell connected to a second channel structure; a peripheral circuit for performing a program operation of storing data in the first and second memory cells commonly connected to a word line; and a program operation controller for controlling the peripheral circuit to perform the program operation, the program operation including an intermediate program operation performed on the first memory cell and then on the second memory cell, and a final program operation preformed to have a threshold voltage of the first and second memory cells to a threshold voltage corresponding to a target program state.

Abstract: A memory device and a method of manufacturing the memory device are described. The memory device includes a connection structure formed on a substrate, lower contacts formed on the connection structure, upper contacts formed on the lower contacts, a dummy pattern configured to enclose the lower contacts and spaced apart from the lower contacts, etching stop patterns formed in an upper region of the dummy pattern, and dummy contacts formed over the etching stop patterns.

Abstract: A memory device includes a cell area and a contact area extending from the cell area in a first direction. The contact area includes a stepped structure arranged along a second direction that intersects the first direction. The memory device also includes a support pattern separating the contact area into a first contact area coupled to the cell area and a second contact area separated from the cell area by the support pattern. The support pattern may include sub-support patterns extending in the first direction and contacting both sides of the second contact area. At least one of the sub-support patterns overlaps at least a portion of the stepped structure, and the second contact area does not overlap with the stepped structure.

Abstract: An electronic device includes a count signal generation circuit configured to increase one of the values of a weak cell count signal and an active count signal by comparing a weak cell address with an adjacent address generated from a row address, when an active operation is performed. The electronic device also includes a target refresh control circuit configured to latch the adjacent address based on the values of the weak cell count signal and the active count signal and to output the latched adjacent address as a target address for a refresh operation based on a target refresh signal.

Abstract: A memory module includes a module substrate, a plurality of memory devices, a first power line, and a second power line. The memory devices are mounted on the module substrate. Each of the memory devices includes a power management member. The first power line may be arranged in the module substrate to provide each of the memory devices with power. The second power line may be electrically connected between the power management members of adjacent memory devices to control and share the power provided to the adjacent memory devices.

Abstract: A memory device includes: a memory cell array including a cell string including a plurality of memory cells respectively connected between a common source line and a plurality of bit lines; a peripheral circuit for performing an internal operation on the memory cells; and control logic for controlling the peripheral circuit to apply a voltage necessary for the internal operation to word lines connected to the plurality of memory cells. The peripheral circuit includes a pass voltage information generator for generating pass voltage information including a number of clocks input from a time at which a pass voltage is applied to the word lines to a time at which a voltage level of the common source line reaches a predetermined reference level. The control logic includes a pass voltage determiner for determining a pass voltage to be applied to the word lines, based on the pass voltage information.

Abstract: The present technology may include a voltage generation circuit configured to generate a plurality of voltages in response to at least one voltage control signal, and control logic configured to generate the at least one voltage control signal in order to adjust at least one of an under drive time and an under drive offset during an under drive operation of a semiconductor apparatus according to a temperature information signal and a pre-stored temperature characteristic signal of the semiconductor apparatus.

Abstract: An image sensing device includes a first substrate including a first front surface and a first back surface, a first interlayer insulation layer disposed below the first front surface and including a first interconnect, a second substrate including a second front surface and a second back surface, a second interlayer insulation layer disposed over the second front surface and below the first interlayer insulation layer to be in contact with the first interlayer insulation layer, and including a second interconnect, a first TSV disposed in a through hole formed by penetrating the first substrate and the first interlayer insulation layer and by etching of a portion of the second interlayer insulation layer, and electrically connecting the first interconnect to the second interconnect, and a passivation layer formed to cover the first TSV. An upper end of the first TSV is located at a height lower than the first back surface.

Abstract: A memory device may include an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers that are alternately stacked on a substrate; a trench in the electrode structure, and having an upper sidewall, a lower sidewall and a horizontal portion that couples the upper sidewall to the lower sidewall and that is parallel to a top surface of the substrate; a dielectric layer in the trench; and a slimming hole in the electrode structure having a sidewall of the trench and a region of the dielectric layer, and having a bottom surface disposed on an electrode layer on which the horizontal portion of the trench is positioned.

Abstract: A memory device, and a method of operating the memory device, includes a memory block including strings formed between bit lines and a source line and includes a peripheral circuit configured to perform a read operation of a selected memory cell included in a selected string among the strings. The peripheral circuit includes page buffers configured to increase a voltage of channels of the strings by applying a first precharge voltage to the bit lines in a set-up phase of the read operation, apply a second precharge voltage lower than the first precharge voltage to the bit lines in a read phase of the read operation, and discharge the bit lines in a discharge phase of the read operation.

Abstract: Disclosed is an image sensor including a pixel array having a pixel pattern in which first to fourth 2×2 pixel groups are arranged in a clockwise direction, one infrared pixel is arranged in each of two 2×2 pixel groups that are not adjacent to each other, the same green pixels are arranged in a first diagonal direction, and red pixels and blue pixels are arranged in half in a second diagonal direction crossing the first diagonal direction, in a 4×4 unit pixel group.

Abstract: A memory controller includes: an initiation queue for storing identification information corresponding to read data of which preparation for transfer to outside the memory controller has started, in response to read requests received from the outside; a completion queue for storing identification information corresponding to read data of which preparation for transfer to the outside is complete; and a data package generator for generating hint information, based on information stored in the initiation queue and the completion queue, generating a data packet including the hint information and first read data of which preparation for transfer is complete, and transferring the data packet to the outside. The hint information may include information on second read data to be transferred to the outside subsequently to the first read data.

Abstract: A page buffer circuit including a data latch circuit and a sensing latch circuit. The data latch circuit configured to store data corresponding to a normal operation. The sensing latch circuit configured to receive and store the data in the data latch circuit in an entering operation in accordance with a suspend operation. The sensing latch circuit configured to transmit the data stored in the sensing latch circuit to the data latch circuit in a sensing operation in accordance with the suspend operation. The sensing latch circuit configured to suspend data in a memory cell, and to output the suspend data from the memory cell.

Abstract: Disclosed is a semiconductor device including a plurality of strings connected between a plurality of bit lines and a source line, a plurality of page buffers connected to the plurality of bit lines, respectively, and configured to adjust a voltage level of each of the plurality of bit lines, and a control circuit configured to control the plurality of page buffers to fix a voltage level of a bit line connected to a string including a memory cell on which a program operation has been completely performed and to change a voltage level of a bit line connected to a string including a memory cell on which the program operation has not been completely performed, during a de-trap operation.

Abstract: A controller controls an operation of a semiconductor memory device based on a request received from a host. The controller includes a host interface, a first function block, a second function block, and an internal command cache. The host interface generates a first internal command in response to the request. The first function block generates a second internal command in response to the first internal command. The second function block operates in response to the second internal command. The internal command cache caches at least one internal command corresponding to a reference internal command.

Abstract: A controller capable of preparing capability information for an interconnection protocol and an electronic device are provided. The controller is for a first device linkable to a second device according to the interconnection protocol. The controller includes a hardware protocol engine and a processing unit. The hardware protocol engine is for implementing a link layer of the interconnection protocol, and capable of performing capability extraction and frame formatting to output capability frame information to a data buffer region and capable of sending, according to content of the data buffer region, a capability frame to the second device during Link Startup Sequence (LSS) capability exchange for the interconnection protocol. The processing unit is configured to be capable of modifying, during the LSS capability exchange, the content of the data buffer region after the capability frame information is output to the data buffer region and before the capability frame is sent to the second device.

Abstract: A semiconductor device includes a stack including a plurality of electrode layers and a plurality of interlayer dielectric layers that are alternately stacked in a vertical direction on a substrate; and a plurality of vertical pass transistors disposed over the stack, and each of the plurality of vertical pass transistors coupled to a corresponding electrode layer, wherein the plurality of vertical pass transistors includes a plurality of first vertical pass transistors and a plurality of second vertical pass transistors, and the plurality of second vertical pass transistors are disposed over the plurality of first vertical pass transistors to be staggered with the plurality of first vertical pass transistors.

Abstract: A semiconductor device including at least one memory cell is provided. The memory cell includes: a first electrode layer; a second electrode layer; a selection element layer coupled between the first electrode layer and the second electrode layer; and an insulating layer coupled between the first electrode layer and the second electrode such that a side surface of the insulating layer is in contact with a side surface of the selection element layer, wherein the selection element layer includes an insulating material doped with a first element, and wherein the insulating layer includes the insulating material doped with the first element at a lower concentration than the selection element layer, or the insulating material not doped with the first element.