Abstract: A semiconductor device includes a selection signal generation circuit configured to generate a selection signal by comparing a first input signal and a second input signal. The semiconductor device also includes a comparison signal generation circuit configured to output a comparison signal by selecting one of the first input signal and the second input signal based on the selection signal.
Abstract: A semiconductor device includes bit lines and a common source line connected to a memory cell array, wherein the bit lines and the common source line are spaced apart from each other in a first level; a pad pattern spaced apart from the bit lines and the common source line in the first level; a first insulating layer covering the bit lines, the common source line, and the pad pattern; a shielding pattern overlapping with the bit lines and disposed on the first insulating layer; a first upper line and a second upper line spaced apart from each other above the shielding pattern; a plurality of contact plugs extending from the first and second upper lines toward the bit lines, common source line, and pad pattern, wherein one or more of the plurality of contact plugs connect the shielding pattern to the second upper line.
Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device includes a memory cell, a page buffer coupled to the memory cell through a bit line and configured to perform a read operation of sensing data stored in the memory cell, wherein the page buffer includes a data storage configured to store data sensed from the memory cell, the read operation includes a precharge period during which a precharge voltage is applied to the bit line, an evaluation period during which a state of the memory cell is incorporated into a voltage of the bit line, and a data storage period during which the data sensed through the bit line is stored in the data storage, and the data storage is initialized during the evaluation period.
Abstract: A data storage device includes a nonvolatile memory device and a memory having an unmap command queue configured to store an unmap command received from a host, and a sequential unmap table configured to store a sequential unmap entry corresponding to an unmap command for sequential logical addresses, and a controller including a first core and a second core. The second core configured to read an unmap-target map segment including the sequential logical addresses from an address mapping table stored in the nonvolatile memory device, store the read unmap-target map segment in the memory, and change, within the stored unmap-target map segment, physical addresses mapped to the sequential logical addresses to trim instruction data at the same time, the trim instruction data being included in the sequential map entry.
Abstract: A controller controlling a memory device includes an elapsed time calculator suitable for receiving an absolute time from a host whenever a state is changed between an active state and an inactive state, calculating an average hibernation elapsed time for elapsed times between first and second absolute times, and calculating a system time based on a third absolute time and the average hibernation elapsed time, and a flash translation layer suitable for controlling a program operation for the memory device in response to a program command for a memory region, calculating a program operation time for the memory region based on the system time, and controlling a read operation for the memory device using a read voltage, which is determined based on an elapsed time since the program operation time, in response to a read command for the memory region.
Abstract: A memory system may include a first memory device including a first input/output buffer, a second memory device including a second input/output buffer, and a cache memory suitable for selectively and temporarily storing first and second data to be respectively programmed in the first and second memory devices. The first data is programmed to the first memory device in a first program section by being stored in the cache memory only in a first monopoly section of the first program section. The second data is programmed to the second memory device in a second program section by being stored in the cache memory only in a second monopoly section of a second program section. The first monopoly section and the second monopoly section are set not to overlap each other.
Abstract: A smart vehicle system is disclosed, which relates to technology for increasing efficiency of a vehicle-embedded memory. The smart vehicle system includes a host and a storage device. The host selects any one of a first mode and a second mode according to operation, process or workload of a vehicle, and transmits and receives data through different channels in response to the first mode and the second mode. The storage device stores the data received through different channels in the first core circuit and the second core circuit, or reads the data stored in the first core circuit and the second core circuit. The storage device executes different operations in the first mode and the second mode in a manner that an operation to be executed in the first mode is different from an operation to be executed in the second mode.
Abstract: A semiconductor apparatus may include a storage device including a data area and a code area and storing program codes provided from a host device in the code area, a plurality of unit processors, each of the plurality of unit processors including an internal memory, and a main control component configured to receive an operation policy, which includes a processor ID, a code ID, and a code address, from the host device and to control the plurality of unit processors based on the operation policy. The processor ID is an identifier for each of the plurality of unit processors, the code ID is an identifier for each of the program codes, and the code address indicates a position of the code area where each of the program codes is stored.
Abstract: Memory controllers, decoders and methods execute a hybrid decoding scheme with exchange of information between multiple decoders. A first type of decoder performs initial decoding of a codeword when an unsatisfied check (USC) count of the codeword is less than a threshold, and a second type of decoder performs decoding of a codeword when the USC count of the codeword is greater than or equal to the threshold. During decoding by one of the decoders, the controller generates information from an output of that decoder and send the information to the other decoder, which the other decoders uses in decoding. The codeword is routed and rerouted between the decoders, which may include a q-bit bit-flipping (q-BF) decoder and a min-sum (MS) decoder, based on conditions that occur during decoding.
Abstract: A control method of a storage device may include the steps of determining, by a storage device controller of the storage device, whether the storage device has to move internal data; deciding, by the storage device controller, a data movement allocation ratio based on at least some of internal data movement requests and the number of free pages in the storage device, when it is determined that the storage device has to move internal data; and allocating, by the storage device controller, one or more programming times to complete a first data number of internal data movement operations corresponding to at least some of the internal data movement requests and a second data number of host data write operations, such that the ratio of the first and second data numbers coincides with the data movement allocation ratio.
Abstract: A data processing system includes a memory device; buffer entries each including a plurality of slabs; a prefetch circuit configured to prefetch data from the memory device and store the data in the buffer entries; and processing circuits respectively corresponding to the slabs, each processing circuit being configured to sequentially demand-fetch and process data stored in corresponding slabs in the buffer entries, wherein each processing circuit checks, when demand-fetching data from a first slab among corresponding slabs, a prefetch trigger bit of a first buffer entry in which the first slab is included, determines, when it is determined that the prefetch trigger bit is set, whether all data stored in the slabs included in a second buffer entry is demand-fetched, and triggers, when it is determined that all the data is demand-fetched, the prefetch circuit to perform prefetch of subsequent data to the second buffer entry.
October 2, 2019
Date of Patent:
July 20, 2021
SK hynix Inc., Purdue Research Foundation
Il Park, T. N. Vijaykumar, Mithuna S Thottethodi, Nitin Delhi
Abstract: The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller configured to generate a command for controlling the memory device and output the command to the memory device. The interface circuit receives the command, transmits the received command to the semiconductor memory when the received command corresponds to the semiconductor memory, and performs a training operation of the interface circuit when the received command corresponds to the interface circuit and the received command is a specific command.
November 11, 2019
Date of Patent:
July 20, 2021
SK hynix Inc.
Chang Kyun Park, Young Sik Koh, Seung Jin Park, Dong Hyun Lee
Abstract: A semiconductor memory includes: first column lines extending in a first direction; first row lines extending in a second direction; first memory cells located between the first row lines and the first column lines; second column lines electrically connected to the first column lines; second row lines extending in the second direction; and second memory cells located between the second row lines and the second column lines. The first column lines and the second column lines may overlap with each other in a third direction. In a first region, current paths on the second row lines are shorter than current paths on the second row lines in a second region. An overlapping ratio of a second column line belonging to the first region with a first column line may be smaller than that of a second column line belonging to the second region with another first column line.
Abstract: A metal option structure of a semiconductor device may include: a plurality of vias connecting first metal lines provided in a first metal layer to second metal lines provided in a second metal layer disposed over the first metal layer, and configured to constitute a plurality of nodes of an option circuit; and an identification pattern disposed between the first and second metal layers and having a different layout structure from the vias.
Abstract: An image sensing device includes a pixel suitable for outputting a pixel signal through a read-out line during a read-out section and a precharge block suitable for precharging the read-out line to a voltage level corresponding to an initial voltage level of the pixel signal during a row non-selection section adjacent to the read-out section.
Abstract: A memory system includes a nonvolatile memory device, a buffer memory device storing logical-physical address mapping information, and a memory controller controlling operations of the nonvolatile and buffer memory devices. The memory controller comprises a cache memory, a host control circuit, a flash translation section, and a flash control circuit. The host control circuit receives a read command and a read logical address from a host, reads mapping information corresponding to the read logical address from the buffer memory device, and caches the mapping information in the cache memory, the mapping information corresponding to the logical-physical address mapping information stored in the buffer memory device. The flash translation section reads a read physical address mapped to the read logical address from the mapping information. The flash control circuit reads data corresponding to the read command from the nonvolatile memory device based on the read physical address.
Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.
March 26, 2021
July 15, 2021
SK hynix Inc.
Ki Won LEE, Seok Man HONG, Tae Hoon KIM, Hyung Dong LEE
Abstract: A semiconductor package includes a package substrate, a die stack having a first sub-stack part and a second sub-stack part, an interface chip, and a bonding wire structure. The bonding wire structure includes a first signal wire connecting first signal die pads included in the first sub-stack part to each other, a first signal extension wire connecting the first signal wire to the interface chip, a second signal wire connecting second signal die pads included in the first sub-stack part to each other, a second signal extension wire connecting the second signal wire to the interface chip, an interpose wire connecting interpose die pads included in the first and second sub-stack parts to each other and electrically connecting the interpose die pads to the interface chip, and a shielding wire branched from the interpose wire.
Abstract: A memory apparatus may include at least one memory, and a memory controller configured to receive an address signal and a command through shared pins and store data, provided from an external source, within the memory controller when a write command is inputted without the address signal.
Abstract: A memory module may include a power source, a memory device, and a power controller. The power source provides at least one power supply voltage. The memory device operates by being supplied with at least one memory power supply voltage. The power controller supplies the at least one memory power supply voltage by changing a voltage level of the at least one power supply voltage based on operation modes of the memory device.