Patents Assigned to SK Hynix Inc.
  • Patent number: 11061614
    Abstract: An electronic apparatus includes a storage device having a plurality of memory blocks including a first memory block; and a controller configured to control the storage device to perform a read operation for the first memory block in response to a read request of a host. The controller controls the storage device to perform a refresh operation for the first memory block based on whether there is a difference value between a current pass read voltage and a previous pass read voltage which were applied to the first memory block when performing the read operation, and whether there is a difference between a current erase/write count and a previous erase/write count for the first memory block.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Chui Sung Kang
  • Patent number: 11061616
    Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a target block manager configured to store a target block address on which a refresh operation is to be performed and output a refresh signal for the target block corresponding to the target block address when an auto refresh command is received, and a data transmission controller configured to output a transmission signal and a buffer control signal for transmitting data between the target block or the buffer block and the temporary buffer circuit in response to the refresh signal.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Won Jae Choi, Ki Chang Gwon
  • Publication number: 20210209022
    Abstract: A PIM device includes a plurality of first storage regions, a second storage region, and a column control circuit. The second storage region is coupled to each of the plurality of first storage regions through a data transmission line. The column control circuit generates a memory read control signal for reading data stored in an initially selected storage region of the plurality of first storage regions and a buffer write control signal for writing the data read from the initially selected storage region to the second storage region. The column control circuit generates a global buffer read control signal for reading the data written to the second storage region and a memory write control signal for writing the data read from the second storage region to a subsequently selected storage region of the plurality of first storage regions.
    Type: Application
    Filed: December 30, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208884
    Abstract: A MAC operator includes a plurality of data type converters and a plurality of multipliers. Each of the plurality of data type converters may receive 16-bit input data of one of first to fourth data types of a floating-point format to convert into L-bit output data of the floating-point format. Each of the plurality of multipliers may perform a multiplication on the “L”-bit output data of the floating-point format outputted from two of the plurality of data type converters to output multiplication result data of the floating-point format.
    Type: Application
    Filed: March 1, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210125
    Abstract: A processing-in-memory (PIM) system includes a host and a PIM controller. The host is configured to generate a request for a memory access operation or a multiplication/accumulation (MAC) operation of a PIM device and also to generate a mode definition signal defining an operation mode of the PIM device. The PIM controller is configured to generate a command corresponding to the request to control the memory access operation or the MAC operation of the PIM device. When the operation mode of the PIM device is inconsistent with a mode set defined by the mode definition signal, the PIM controller controls the memory access operation or the MAC operation of the PIM device after changing the operation mode of the PIM device.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210551
    Abstract: A resistive memory device includes a vertical word line pillar, a plurality of resistive layers, a gate insulation layer, and a channel layer. The vertical word line pillar is formed on a semiconductor substrate. The resistive layers are stacked at both sides of the vertical word line pillar. The gate insulation layer is interposed between the vertical word line pillar and the resistive layers. The channel layer is arranged between the gate insulation layer and the resistive layers.
    Type: Application
    Filed: June 29, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Jae Hyun Han
  • Publication number: 20210208878
    Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a multiplier for performing a multiplying calculation of the first data and the second data. The arithmetic circuit is configured to perform a multiplication/accumulation (MAC) arithmetic operation of the first data and the second data. The arithmetic circuit includes a zero-detection circuit configured to disable input of the multiplier and to output zero data including multiple bits having a value of ‘0’ as output data of the multiplier, when all bits included in at least one of the first data and the second data have a value of ‘0’.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventors: Mun Gyu SON, Choung Ki SONG
  • Publication number: 20210209455
    Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators and a plurality of memory banks. The MAC operators are included in each of a plurality of channels. Each of the plurality of MAC operators performs a MAC arithmetic operation using weight data of a weight matrix. The memory banks are included in each of the plurality of channels and are configured to transmit the weight data of the weight matrix to the plurality of MAC operators. The weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208881
    Abstract: A neural network system includes a data type converter and a MAC operator. The data type converter may convert 32-bit floating-point format into one of a plurality of 16-bit floating-point formats. The MAC operator may perform MAC operations using 16-bit floating-point format data converted by the data type converter. The MAC operator includes a data type modulator configured to modulate the bit number of the converted 16-bit floating-point format to provide a modulated floating-point format with bit number different from the bit number of the converted 16-bit floating-point format.
    Type: Application
    Filed: February 12, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208817
    Abstract: A memory system includes a plurality of memory dies respectively having at least one channel, a controller configured to control the plurality of memory dies, and a base die configured for interfacing signal and data transmissions between the plurality of memory dies and the controller. The controller is configured to remap a logical channel address of the most frequently used channel to a physical channel address of a channel having a lowest temperature value to transmit the remapped physical channel address to the base die.
    Type: Application
    Filed: January 13, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventors: Woo Jae SHIN, Choung Ki SONG
  • Publication number: 20210208894
    Abstract: A PIM device writes elements of a first matrix to a first memory bank, and may writes elements of a second matrix to a second memory bank. The PIM device simultaneously reads elements with the same order among the elements of the first and second matrices by simultaneously accessing the first and second memory banks. An MAC operator generates arithmetic data by performing a calculation on data that is read from the first and second memory banks, and writes the arithmetic data to a third memory bank.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208882
    Abstract: A MAC operator includes a plurality of multipliers, a plurality of floating-point to fixed-point converters, an adder tree, an accumulator, and a fixed-point to floating-point converter. Each of the plurality of multipliers may perform a multiplication operation on first data and second data of a single-precision floating-point (FP32) format to output multiplication result data of the FP 32 format. Each of the plurality of floating-point to fixed-point converters may convert the FP 32 format into a fixed-point format. The adder tree may perform a first addition operation on the data of the fixed-point format. The accumulator may perform an accumulation operation on the data output from the adder tree. And the fixed-point to floating-point converter may convert the data of the fixed-point format into data of the FP32 format.
    Type: Application
    Filed: February 12, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210458
    Abstract: A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.
    Type: Application
    Filed: June 12, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Chan Sun LEE
  • Publication number: 20210208816
    Abstract: A processing-in-memory (PIM) device includes a first group of storage regions, a second group of storage regions, and a plurality of multiplication/accumulation (MAC) operators. The MAC operators are configured to communicate with the first and second groups of storage regions through a global data input/output (GIO) line. A first storage region corresponding to a storage region of the first group of storage regions, a second storage region corresponding to a storage region of the second group of storage regions, and a first MAC operator corresponding to a MAC operator of the plurality of MAC operators constitute a MAC unit. The first MAC operator is configured to receive first data and second data from the first and second storage regions, respectively, through the GIO line to perform a MAC arithmetic operation of the first and second data and to output a result of the MAC arithmetic operation.
    Type: Application
    Filed: November 5, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210426
    Abstract: A semiconductor memory device includes a channel structure extending in a first direction, a source select line surrounding the channel structure and including a groove, interlayer insulating films and word lines surrounding the channel structure, wherein the interlayer insulating films and the word lines are alternately stacked on the source select line in the first direction, and a first contact plug extending into the source select line through the groove.
    Type: Application
    Filed: July 1, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20210208885
    Abstract: A processing-in-memory (PIM) device includes a data selection circuit, a multiplying-and-accumulating (MAC) circuit, and an accumulative adding circuit. The data selection circuit generates selection data from input data and zero-point data based on a zero-point selection signal. The MAC circuit performs a MAC arithmetic operation for the selection data to generate MAC result data. The accumulative adding circuit accumulatively adds MAC sign data based on a MAC output latch signal to generate MAC latch data. A sign of the MAC sign data is determined by the zero-point selection signal.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210146
    Abstract: An electronic device includes drain select lines, source select lines, a plurality of word lines arranged between the drain select lines and the source select lines, and a peripheral circuit configured to perform a program operation on selected memory cells connected to a selected word line among the plurality of word lines. The peripheral circuit includes a voltage generator configured to generate a voltage for initializing a channel of a plurality of memory cells respectively connected to the plurality of word lines in a program phase among a plurality of phases included in the program operation.
    Type: Application
    Filed: June 30, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Hee Joo LEE
  • Publication number: 20210208814
    Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.
    Type: Application
    Filed: September 21, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210123
    Abstract: A memory system includes a stacked memory device and a controller. The stacked memory device includes a base die and a plurality of memory dies stacked on the base die. Each of the plurality of memory dies has a plurality of channels, and the base die is configured to function as an interface for transmitting signals and data of the pluralities of channels. The controller controls the stacked memory device such that first and second data move control operations are sequentially performed to transmit moving data from a target channel of the pluralities of channels to a destination channel of the pluralities of channels. The first data move control operation is performed to store the moving data in the target channel into the base die, and the second data move control operation is performed to write the moving data stored in the base die into the destination channel.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210145
    Abstract: A semiconductor memory device, and a method of operating the semiconductor memory device, includes a memory cell array including a plurality of normal memory blocks and at least one system block, and a peripheral circuit configured to perform a program operation, a read operation, or an erase operation on the plurality of normal memory blocks or the at least one system block, wherein a data storage capacity of the at least one system block is less than a data storage capacity of each of the plurality of normal memory blocks.
    Type: Application
    Filed: July 7, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Sang Bum LEE