Abstract: A method of producing a structure made of a piezoelectric material, including: a) production of a stack including at least one metal layer and at least one conductive layer on a substrate made of piezoelectric material, wherein at least one electrical contact is established between the conductive layer and a metal element outside the stack; b) an ionic and/or atomic implantation, through the conductive layer and the metal layer; c) transfer of the substrate onto a transfer substrate, followed by fracturing of the transferred piezoelectric substrate, in an embrittlement area.
Type:
Application
Filed:
July 5, 2011
Publication date:
May 9, 2013
Applicants:
SOITEC, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
Inventors:
Chrystel Deguet, Nicolas Blanc, Bruno Imbert, Jean-Sebastien Moulet
Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer.
Abstract: A three-dimensional composite structure that includes a wafer and layer of semiconductor crystalline material bonded thereto, with the layer including first and second series of microcomponents on the first and second faces respectively, with the microcomponents being in alignment such that any residual alignment offsets between the first and second series of microcomponents are less than 100 nm homogeneously over the entire surface of the structure.
Abstract: A system for epitaxial deposition of a Group III-V semiconductor material that includes gallium. The system includes sources of the reactants, one of which is a gaseous Group III precursor having one or more gaseous gallium precursors and another of which is a gaseous Group V component, a reaction chamber wherein the reactants combine to deposit Group III-V semiconductor material, and one or more heating structures for heating the gaseous Group III precursors prior to reacting to a temperature to decompose substantially all dimers, trimers or other molecular variations of such precursors into their monomer forms.
Abstract: A semiconductor growth system includes a chamber and a source of electromagnetic radiation. A detector is arranged to detect absorption of radiation from the source by a chloride- based chemical of the reaction chamber. A control system controls the operation of the chamber in response to the absorption of radiation by the chloride-based chemical. The control system controls the operation of the chamber by adjusting a parameter of the reaction chamber.
Type:
Grant
Filed:
July 21, 2009
Date of Patent:
April 30, 2013
Assignee:
Soitec
Inventors:
Ronald Thomas Bertram, Jr., Chantal Arena, Christiaan J. Werkhoven, Michael Albert Tischler, Vasil Vorsa, Andrew D. Johnson
Abstract: The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.
Abstract: The invention relates to a structure and a process for measuring an energy of adhesion between two substrates bonded in a transverse direction. The method involves providing for at least one of the two substrates to have a plurality of elementary test cells within a test layer each being capable of locally applying, in the transverse direction, a preset mechanical stress (?), dependent on the temperature (T), to a bond interface between the substrates in a direction tending to separate them, applying a test temperature to the substrates and identifying debonded regions of the bond interface so that the local adhesion energy at the test temperature in the regions may be deduced therefrom, the local adhesion energy in a region of the bond interface being deduced from the stress applied by the test cells that caused debonding in the region.
Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.
Abstract: A process for cleaving a substrate for the purpose of detaching a film therefrom. The method includes the formation of a stress-generating structure locally bonded to the substrate surface and designed to expand or contract in a plane parallel to the substrate surface under the effect of a heat treatment; and the application of a heat treatment to the structure, designed to cause the structure to expand or contract so as to generate a plurality of local stresses in the substrate which generates a stress greater than the mechanical strength of the substrate in a cleavage plane parallel to the surface of the substrate defining the film to be detached, the stress leading to the cleavage of the substrate over the cleavage plane. Also, an assembly of a substrate and the stress-generating structure as well as use of the assembly in a semiconductor device for photovoltaic, optoelectronic or electronic applications.
Abstract: The invention relates to a method of producing a semiconductor structure by transferring a layer of a donor substrate to a receiver substrate, with the creation of an embrittlement zone in the donor substrate to define the transfer layer, and the treatment of the surface of one of the substrates to increase the bonding strength between them, followed by the direct wafer bonding of the substrates and the detachment of the donor substrate at the embrittlement zone to form the semiconductor structure, in which the surface of the receiver substrate, except for a peripheral crown, is covered with the transferred layer. The treatment of the substrate surface is controlled so that the bonding strength between the substrates is lower in a peripheral area than in a central area. The peripheral area has a width at least equal to the that of the crown and less than 10 mm.
Type:
Grant
Filed:
September 11, 2008
Date of Patent:
April 16, 2013
Assignee:
Soitec
Inventors:
Brigitte Soulier-Bouchet, Sébastien Kerdiles, Walter Schwarzenbach
Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
Abstract: A method for preparing a substrate for detaching a layer by irradiation of the substrate with a light flux for heating a buried region of the substrate and bringing about decomposition of the material of that region to detach said detachment layer. The method includes fabricating an intermediate substrate including a first buried layer, and a second covering layer that covers all or part of the first layer, with the covering layer being substantially transparent to the light flux and with the buried layer formed by implantation of particles into the substrate, followed by absorbing the flux, and selectively and adiabatically irradiating a treated region of the buried layer until at least partial decomposition of the material constituting it ensues.
Abstract: A method for reducing irregularities at the surface of a layer transferred from a source substrate to a glass-based support substrate, by generating a weakening zone in the source substrate; contacting the source substrate and the glass-based support substrate; and splitting the source substrate at the weakening zone; wherein the glass-based substrate has a thickness of between 300 ?m and 600 ?m.
Type:
Application
Filed:
June 20, 2011
Publication date:
March 21, 2013
Applicant:
SOITEC
Inventors:
Daniel Delprat, Carine Duret, Nadia Ben-Mohamed, Fabrice Lallement
Abstract: An InGaN-on-substrate structure that includes an InGaN layer and two mirror layers on opposing sides of and sandwiching the InGaN layer. The InGN layer includes an InGaN seed layer and an active InGaN layer grown on the InGaN seed layer. Such a structure is useful in a vertical optoelectronic device.
Abstract: The present invention relates to the field of semiconductor processing and provides apparatus and methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the invention comprises heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention comprises radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases.
Type:
Grant
Filed:
October 30, 2008
Date of Patent:
March 5, 2013
Assignee:
Soitec
Inventors:
Chantal Arena, Christiaan J. Werkhoven, Ronald Thomas Bertram, Jr., Ed Lindow
Abstract: A method for making a semiconductor on insulator (SeOI) type substrate that includes an integrated ground plane under the insulating layer wherein the substrate is intended to be used in making electronic components. This method includes implanting atoms or ions of a metal in at least one portion of a semiconducting receiver substrate, carrying out a heat treatment of the receiver substrate in order to obtain an integrated ground plane on or in at least one portion of that receiver substrate, transferring an active layer stemming from a semiconducting donor substrate onto the receiver substrate, with an insulating layer being inserted in between the donor and receiver substrates to obtain the substrate with an integrated ground plane.
Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.
Type:
Grant
Filed:
March 17, 2010
Date of Patent:
March 5, 2013
Assignee:
Soitec
Inventors:
Walter Schwarzenbach, Sébastien Kerdiles, Patrick Reynaud, Ludovic Ecarnot, Eric Neyret
Abstract: Methods of depositing compound semiconductor materials on one or more substrates include metering and controlling a flow rate of a precursor liquid from a precursor liquid source into a vaporizer. The precursor liquid may comprise at least one of GaCl3, InCl3, and AlCl3 in a liquid state. The precursor liquid may be vaporized within the vaporizer to form a first precursor vapor. The first precursor vapor and a second precursor vapor may be caused to flow into a reaction chamber, and a compound semiconductor material may be deposited on a surface of a substrate within the reaction chamber from the precursor vapors. Deposition systems for performing such methods include devices for metering and/or controlling a flow of a precursor liquid from a liquid source to a vaporizer, while the precursor liquid remains in the liquid state.
Abstract: Deposition systems include a reaction chamber, at least one thermal radiation emitter for heating matter within the reaction chamber, and at least one metrology device for detecting and/or measuring a characteristic of a workpiece substrate in situ within the reaction chamber. One or more chamber walls may be transparent to the thermal radiation and to radiation signals to be received by the metrology device, so as to allow the radiation to pass into and out from the reaction chamber, respectively. At least one volume of opaque material is located to shield a sensor of the metrology device from at least some of the thermal radiation. Methods of forming a deposition system include providing such a volume of opaque material at a location shielding the sensor from the thermal radiation. Methods of using a deposition system include shielding the sensor from at least some of the thermal radiation.
Type:
Application
Filed:
December 15, 2011
Publication date:
February 28, 2013
Applicant:
SOITEC
Inventors:
Ed Lindow, Ronald Bertram, Claudio Canizares