Patents Assigned to Soitec
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Publication number: 20140020732Abstract: The present invention relates to a solar cell array configuration comprising a plurality of solar cells provided on at least one substrate, a plurality of contact pads, one contact pad for each of the plurality of solar cells, provided on the at least one substrate, electrical wiring connecting each of the plurality of solar cells with a corresponding one of the plurality of contact pads and a diode electrically connected with at least two of the plurality of solar cells.Type: ApplicationFiled: February 23, 2012Publication date: January 23, 2014Applicant: SOITEC SOLAR GMBHInventors: Eckart Gerster, Martin Ziegler
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Publication number: 20140015023Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.Type: ApplicationFiled: September 16, 2013Publication date: January 16, 2014Applicant: SoitecInventors: Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure, Mohamad A. Shaheen
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Publication number: 20140014029Abstract: A method of preventing microcavity formation in the bonding layer of a composite structure resulting from creep and thermal expansion due to high temperature exposure of the composite structure The method includes the steps of providing the thin film with a thickness of 5 micrometers or less; providing the bonding layer of oxide with a thickness that is equal to or greater than the thickness of the thin film with the bonding layer formed by low pressure chemical vapor deposition. The thin film or support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The thin film, bonding layer and support substrate combine to reduce stress in and plastic deformation of the bonding layer during exposure to during exposure to high temperatures of more than approximately 900° C. to thus prevent microcavities from appearing in the bonding layer.Type: ApplicationFiled: September 19, 2013Publication date: January 16, 2014Applicant: SOITECInventors: Bruce FAURE, Alexandra MARCOVECCHIO
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Patent number: 8628674Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.Type: GrantFiled: November 20, 2012Date of Patent: January 14, 2014Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, SoitecInventors: Marc Zussy, Bernard Aspar, Chrystelle Lagahe-Blanchard, Hubert Moriceau
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Patent number: 8623740Abstract: A method for producing a structure having an ultra thin buried oxide (UTBOX) layer by assembling a donor substrate with a receiver substrate wherein at least one of the substrates includes an insulating layer having a thickness of less than 50 nm that faces the other substrate, conducting a first heat treatment for reinforcing the assembly between the two substrates at temperature below 400° C., and conducting a second heat treatment at temperature above 900° C., wherein the exposure time between 400° C. and 900° C. between the heat treatments is less than 1 minute and advantageously less than 30 seconds.Type: GrantFiled: October 29, 2009Date of Patent: January 7, 2014Assignee: SoitecInventors: Didier Landru, Ionut Radu, Sébastien Vincent
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Patent number: 8625374Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.Type: GrantFiled: December 18, 2012Date of Patent: January 7, 2014Assignee: SoitecInventors: Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen
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Publication number: 20140001604Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Applicant: SOITECInventor: Mariam Sadaka
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Publication number: 20140001642Abstract: Interposers for use in the fabrication of electronic devices include semiconductor-on-insulator structures having fluidic microchannels therein. The interposers may include a multi-layer body in which a semiconductor material is bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel may extend in a lateral direction through at least one of the layer of dielectric material and the semiconductor material. The interposers may include redistribution layers and electrical contacts on opposing sides thereof. Semiconductor structures include one or more semiconductor devices coupled with such interposers. Such interposers and semiconductor structures may be formed by fabricating a semiconductor-on-insulator type structure using a direct bonding method and defining one or more fluidic microchannels at a bonding interface during the direct bonding process.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Applicant: SOITECInventor: Mariam Sadaka
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Patent number: 8617962Abstract: The invention relates to finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two semiconducting material layers. The method successively comprises routing the annular periphery of the substrate so as to obtain a routed substrate, and encapsulating the routed substrate so as to cover the routed side edge of the buried insulator layer by means of a semiconducting material.Type: GrantFiled: March 14, 2011Date of Patent: December 31, 2013Assignee: SoitecInventors: Walter Schwarzenbach, Aziz Alami-Idrissi, Alexandre Chibko, Sebastien Kerdiles
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Patent number: 8617925Abstract: Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods.Type: GrantFiled: August 9, 2011Date of Patent: December 31, 2013Assignee: SoitecInventors: Mariam Sadaka, Bich-Yen Nguyen
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Publication number: 20130341756Abstract: A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film.Type: ApplicationFiled: August 22, 2013Publication date: December 26, 2013Applicants: SOITEC, CORNING INCORPORATEDInventors: Nadia Ben Mohamed, Ta-Ko Chuang, Jeffrey Scott Cites, Daniel Delprat, Alexander Usenko
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Patent number: 8614501Abstract: A method of producing a layer of cavities in a structure comprises at least one substrate formed from a material that can be oxidized or nitrided, the method comprising the following steps: implanting ions into the substrate in order to form an implanted ion concentration zone at a predetermined mean depth; heat treating the implanted substrate to form a layer of cavities at the implanted ion concentration zone; and forming an insulating layer in the substrate by thermochemical treatment from one surface of the substrate, the insulating layer that is formed extending at least partially into the layer of cavities.Type: GrantFiled: February 1, 2010Date of Patent: December 24, 2013Assignee: SOITECInventor: Didier Landru
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Publication number: 20130327266Abstract: The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.Type: ApplicationFiled: August 14, 2013Publication date: December 12, 2013Applicant: SoitecInventors: Chantal ARENA, Christiaan WERKHOVEN
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Patent number: 8603896Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.Type: GrantFiled: July 26, 2012Date of Patent: December 10, 2013Assignee: SoitecInventors: Gweltaz Gaudin, Carlos Mazure
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Publication number: 20130323861Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.Type: ApplicationFiled: August 2, 2013Publication date: December 5, 2013Applicant: SoitecInventors: Chrystelle Lagahe, Bernard Aspar
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Patent number: 8598019Abstract: Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods.Type: GrantFiled: July 18, 2012Date of Patent: December 3, 2013Assignee: SoitecInventor: Chantal Arena
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Publication number: 20130309841Abstract: The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.Type: ApplicationFiled: July 29, 2013Publication date: November 21, 2013Applicant: SOITECInventors: Sebastien Kerdiles, Daniel Delprat
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Patent number: 8585820Abstract: Methods for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment and methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material.Type: GrantFiled: November 15, 2007Date of Patent: November 19, 2013Assignee: SoitecInventors: Chantal Arena, Christiaan Werkhoven
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Publication number: 20130302970Abstract: A method of transferring a layer from a donor substrate onto a receiving substrate comprises ionic implantation of at least one species into the donor substrate and forming a layer of concentration of the species intended to form microcavities or platelets; bonding the donor substrate with the receiving substrate by wafer bonding; and splitting at high temperature to split the layer in contact with the receiving substrate by cleavage, at a predetermined cleavage temperature, at the layer of microcavities or platelets formed in the donor substrate. The method further comprises, after the first implantation step and before the splitting step, ionic implantation of silicon ions into the donor substrate to form a layer of concentration of silicon ions in the donor substrate, the layer of concentration of silicon ions at least partially overlapping the layer of concentration of the species intended to form microcavities or platelets.Type: ApplicationFiled: November 23, 2011Publication date: November 14, 2013Applicant: SOITECInventors: Nicolas Daix, Konstantin Bourdelle
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Patent number: 8580654Abstract: The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.Type: GrantFiled: September 29, 2011Date of Patent: November 12, 2013Assignee: SoitecInventors: Sébastien Kerdiles, Daniel Delprat