Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, forming electrically conductive emitter plugs and base plugs on the interdigitated pattern, and attaching a backplane having a second interdigitated pattern of base electrodes and emitter electrodes at the conductive emitter and base plugs to form electrical interconnects.
Type:
Grant
Filed:
August 5, 2011
Date of Patent:
February 3, 2015
Assignee:
Solexel, Inc.
Inventors:
Mehrdad M. Moslehi, David Xuan-Qi Wang, Karl-Josef Kramer, Sean M. Seutter, Sam Tone Tor, Anthony Calcaterra
Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects as well as Fabrication methods and structures for forming thin film back contact solar cells are described.
Type:
Application
Filed:
August 9, 2012
Publication date:
January 22, 2015
Applicant:
SOLEXEL, INC.
Inventors:
Mehrdad M. Moslehi, Pawan Kapur, Karl-Josef Kramer, Virendra V. Rana, Sean Seutter, Anand Deshpande, Anthony Calcaterra, Gerry Olsen, Kamran Manteghi, Thom Stalcup, George D. Kamian, David Xuan-Qi Wang, Yen-Sheng Su, Michael Wingert
Abstract: The present disclosure enables high-volume cost effective production of three-dimensional thin film solar cell (3-D TFSC) substrates. First, the present disclosure discloses pyramid-like unit cell structure 16 and 50 which enable epitaxial growth through their open pyramidal structure. The present disclosure than gives four 3-D TFSC embodiments 70, 82, 100, and 110 which may combined as necessary. A basic 3-D TFSC having a substrate, emitter, oxidation on the emitter, front and back metal contacts allows simple processing. Other embodiments disclose a selective emitter, selective backside metal contact, and front-side SiN ARC layers. Several processing methods including process flows 150, 200, 250, 300, and 350 enable production of these 3-D TFSC. Further, the present disclosure enables higher throughput through the use of dual sided template 400. By processing the substrate in the template, the present disclosure increases yield and reduces processing steps.
Abstract: It is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high volume production of photovoltaic (PV) solar cell device architecture. It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon. The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure. Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer.
Type:
Grant
Filed:
January 15, 2010
Date of Patent:
January 6, 2015
Assignee:
Solexel, Inc.
Inventors:
Doug Crafts, Mehrdad Moslehi, Subramanian Tamilmani, Joe Kramer, George D. Kamian, Somnath Nag
Abstract: A three-dimensional thin-film semiconductor substrate with selective through-holes is provided. The substrate having an inverted pyramidal structure comprising selectively formed through-holes positioned between the front and back lateral surface planes of the semiconductor substrate to form a partially transparent three-dimensional thin-film semiconductor substrate.
Abstract: According to one aspect of the disclosed subject matter, a method for forming a monolithically isled back contact back junction solar cell using bulk wafers is provided. Emitter and base contact regions are formed on a backside of a semiconductor wafer having a light receiving frontside and a backside opposite said frontside. A first level contact metallization is formed on the wafer backside and an electrically insulating backplane is attached to the semiconductor wafer backside. Isolation trenches are formed in the semiconductor wafer patterning the semiconductor wafer into a plurality of electrically isolated isles and the semiconductor wafer is thinned. A metallization structure is formed on the electrically insulating backplane electrically connecting the plurality of isles.
Type:
Application
Filed:
February 12, 2014
Publication date:
December 18, 2014
Applicant:
Solexel, Inc.
Inventors:
Mehrdad M. Moslehi, Pawan Kapur, Karl-Josef Kramer, Michael Wingert
Abstract: Methods and structures for photovoltaic back contact solar cells having multi-level metallization with at least one aluminum-silicon alloy metallization layer are provided.
Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
Type:
Grant
Filed:
November 3, 2011
Date of Patent:
December 9, 2014
Assignee:
Solexel, Inc.
Inventors:
Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George Kamian, Jay Ashjaee, Takao Yonehara
Abstract: According to one aspect of the disclosed subject matter, a monolithically isled solar cell is provided. The solar cell comprises a semiconductor layer having a light receiving frontside and a backside opposite the frontside and attached to an electrically insulating backplane. A trench isolation pattern partitions the semiconductor layer into electrically isolated isles on the electrically insulating backplane. A first metal layer having base and emitter electrodes is positioned on the semiconductor layer backside. A patterned second metal layer providing cell interconnection and connected to the first metal layer by via plugs is positioned on the backplane.
Abstract: Fabrication methods and structures relating to multi-level metallization for solar cells as well as fabrication methods and structures for forming thin film back contact solar cells are provided.
Abstract: The present disclosure presents a partially-transparent (see-through) three-dimensional thin film solar cell (3-D TFSC) substrate. The substrate includes a plurality of unit cells. Each unit cell structure has the shape of a truncated pyramid, and its parameters may be varied to allow a desired portion of sunlight to pass through.
Abstract: Solar module structures and methods for assembling solar module structures. The solar module structures comprise pyramidal three-dimensional thin-film solar cells arranged in solar module structures. The pyramidal three-dimensional thin-film solar cell comprises a pyramidal three-dimensional thin-film solar cell substrate with emitter junction regions and doped base regions. The three-dimensional thin-film solar cell further includes emitter metallization regions and base metallization regions. The three-dimensional thin-film solar cell substrate comprises a plurality of pyramid-shaped unit cells. The solar module structures may be used in solar glass applications, building façade applications, rooftop installation applications as well as for centralized solar electricity generation.
Abstract: A three-dimensional thin film solar cell (3-D TFSC) substrate having enhanced mechanical strength, light trapping, and metal modulation coverage properties. The substrate includes a plurality of unit cells, which may or may not be different. Unit cells are defined as a small self-contained geometrical pattern which may be repeated. Each unit cell structure includes a wall enclosing a trench. Further, the unit cell includes an aperture having an aperture diameter. A pre-determined variation in wall thickness, wall height, and aperture diameter among unit cells across the substrate produces specific advantages.
Type:
Grant
Filed:
March 22, 2010
Date of Patent:
September 9, 2014
Assignee:
Solexel, Inc.
Inventors:
David Xuan-Qi Wang, Mehrdad M. Moslehi, Pawan Kapur, Suketu Parikh
Abstract: Methods and structures for extracting at least one electric parametric value from a back contact solar cell having dual level metallization are provided.
Type:
Grant
Filed:
April 23, 2013
Date of Patent:
September 9, 2014
Assignee:
Solexel, Inc.
Inventors:
Swaroop Kommera, Pawan Kapur, Mehrdad M. Moslehi
Abstract: Solar module structures 210 and 270 and methods for assembling solar module structures. The solar module structures 210 and 270 comprise three-dimensional thin-film solar cells 110 arranged in solar module structures 210 and 270. The three-dimensional thin-film solar cell comprises a three-dimensional thin-film solar cell substrate (124 and 122, respectively) with emitter junction regions 1352 and doped base regions 1360. The three-dimensional thin-film solar cell further includes emitter metallization regions and base metallization regions. The 3-D TFSC substrate comprises a plurality of single-aperture or dual-aperture unit cells. The solar module structures 270 using three-dimensional thin-film solar cells comprising three-dimensional thin-film solar cell substrates with a plurality of dual-aperture unit cells may be used in solar glass applications.
Abstract: Non-contact and non-invasive temperature measurement structures and methods for thermal processing systems which neither damage nor contaminate the thermal processing environment are provided.
Abstract: Methods and structures for extracting at least one electric parametric value from a back contact solar cell having dual level metallization are provided.
Type:
Application
Filed:
April 23, 2013
Publication date:
May 29, 2014
Applicant:
Solexel, Inc.
Inventors:
Swaroop Kommera, Pawan Kapur, Mehrdad M. Moslehi
Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate.
Type:
Application
Filed:
July 15, 2013
Publication date:
May 8, 2014
Applicant:
Solexel, Inc.
Inventors:
David Xuan-Qi Wang, Mehrdad M. Moslehi, Somnath Nag
Abstract: Structures and methods for a solar cell having an integrated bypass switch are provided. According to one embodiment, an integrated solar cell and bypass switch comprising a semiconductor layer having background doping, a frontside, and a backside is provided. A patterned first level metal is positioned on the layer backside and an electrically insulating backplane is positioned on the first level metal. A trench isolation pattern partitions the semiconductor layer into a solar cell region and at least one monolithically integrated bypass switch region. A patterned second level metal is positioned on the electrically insulating backplane and which connects to the first level metal through the backplane to complete the electrical metallization of the monolithically integrated solar cell and bypass switch structure.
Abstract: The present disclosure presents a chemical vapor deposition reactor having improved chemical utilization and cost efficiency. The wafer susceptors of the present disclosure may be used in a stackable configuration for processing many wafers simultaneously. The reactors of the present disclosure may be reverse-flow depletion mode reactors, which tends to provide uniform film thickness and a high degree of chemical utilization.