Patents Assigned to ST Assembly Test Services
  • Patent number: 7217599
    Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: May 15, 2007
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Jeffrey D. Punzalan, Jae Hun Ku, Byung Joon Han
  • Patent number: 7205651
    Abstract: A substrate is provided. A first die is attached to the substrate. The first die is electrically connected to the substrate. A heat sink having an undercut around its periphery is attached to the first die. A second die is attached to the heat sink. The second die is electrically connected to the substrate, and the first die, the heat sink, and the second die are encapsulated.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: April 17, 2007
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Byung Tai Do, Byung Hoon Ahn
  • Patent number: 7153725
    Abstract: A method for fabricating a semiconductor package with a substrate in a strip format is provided. Semiconductor devices are attached in a strip format to the substrate, and a thermal interface material is applied to the semiconductor devices. A flat panel heat spreader is attached to each semiconductor device. The semiconductor devices are encapsulated with open encapsulation, leaving the surface of the flat panel heat spreader opposite the substrate externally exposed. Individual semiconductor packages are then singulated from the strip format.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: December 26, 2006
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Tie Wang, Virgil Cotoco Ararao, Il Kwon Shim, Sheila Marie L. Alvarez
  • Patent number: 7135760
    Abstract: A leadframe for a semiconductor die includes signal leads, ground leads, and a die support holder for supporting the semiconductor die. The die support holder has opposite surfaces and side edges therebetween. The opposite die support holder surfaces are smaller in transverse extent than the semiconductor die for supporting the die on one of the opposite die support holder surfaces such that the die extends beyond the side edges of the die support holder.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: November 14, 2006
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Byung Joon Han, Byung Hoon Ahn
  • Patent number: 7129569
    Abstract: A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of the leadfingers.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: October 31, 2006
    Assignee: St Assembly Test Services Ltd.
    Inventors: Jeffrey D. Punzalan, Jose Alvin Caparas, Jae Hun Ku
  • Publication number: 20060197198
    Abstract: A system is provided for an integrated circuit package including a leadframe with a lead finger. A groove is in a lead finger for a conductive bonding agent and a passive device is in the groove to be held by the conductive bonding agent.
    Type: Application
    Filed: December 23, 2005
    Publication date: September 7, 2006
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Seng Guan Chow, Il Kwon Shim, Ming Ying, Byung Hoon Ahn
  • Publication number: 20060197223
    Abstract: An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad.
    Type: Application
    Filed: December 23, 2005
    Publication date: September 7, 2006
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Lun Zhao, Wan Lay Looi, Kyaw Oo Aung, Yonggang Jin, Jae-Yong Song, Won Sun Shin
  • Patent number: 7091469
    Abstract: An optoelectronic sensor is attached to an optically transparent substrate, such as glass, and encapsulated to form an optoelectronic device. An optical assembly can be mounted opposite the optoelectronic sensor. Filters and refractive index matching materials may be included between the optoelectronic sensor and the optically transparent substrate.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: August 15, 2006
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Dean Paul Kossives, Kambhampati Ramakrishna, Edward Lap Zak Law, Diane Sahakian, Theodore G. Tessier, Jamin Ling
  • Patent number: 7091596
    Abstract: Semiconductor packages provide a leadframe for packages that are singulated with respective predetermined package body sizes. Individual mold caps are formed on the leadframe with mold cap dimensions that are larger than the respective predetermined package body sizes. The mold caps and leadframe are singulated to the respective predetermined package body sizes.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: August 15, 2006
    Assignee: St Assembly Test Services Ltd.
    Inventors: Byung Joon Han, Byung Hoon Ahn
  • Patent number: 7081668
    Abstract: An Integrated Circuit package structure includes an Integrated Circuit device having a electrical contact points to the device in the bottom surface. A heatsink has a flat bottom surface extending past the device by a first distance and contacting the top surface of the device. A substrate has a flat upper surface extending past the device by the first distance and having points of electrical contact to the device and a lower surface having points of electrical contact for further interconnect of the substrate to surrounding circuitry or components with the upper and lower surfaces extending beyond the bottom surface of the device. A molding compound is between the flat bottom surface of the heatsink and the flat upper surface of the substrate to fill only the first distance and is among the points of electrical contact to the device.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: July 25, 2006
    Assignee: St Assembly Test Services Pte.
    Inventor: John Briar
  • Patent number: 7076861
    Abstract: The present invention provides a kit and method for package-to-package conversion of a pick and place handler. An input arm assembly is provided with interchangeable vacuum leads such that package-to-package conversion only requires replacing the vacuum lead with a different size vacuum lead. An input/output shuttle plate is provided comprising a block and base plate. The block has a plurality of pocket groupings and a two or more alignment hole groupings. The base plate has two or more alignment pins. Package-to-package conversion is achieved by changing which alignment hole in each alignment hole grouping is set on the alignment pins, thereby selecting the pocket in each pocket grouping corresponding to the alignment hole used. A soak plate is provided having an array of pocket groupings, wherein each pocket grouping has the same pattern of different size/shape pockets to accommodate different packages.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: July 18, 2006
    Assignee: St Assembly Test Services Pte.
    Inventors: Kai Wah Sum, Wee Boon Tan, Liop Jin Yap
  • Patent number: 7064420
    Abstract: A leadframe for a semiconductor package includes signal and ground leads, a ground plane, and a frame paddle. Supports connect the signal and ground leads, ground plane, and frame paddle in at least two different layers. At least one force release and stress relief structure is incorporated into the leadframe to free the ground plane substantially from distortion and warpage resulting from residual mechanical stresses therein.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: June 20, 2006
    Assignee: St Assembly Test Services Ltd.
    Inventors: Byung Joon Han, Byung Hoon Ahn, Zheng Zheng
  • Patent number: 7060536
    Abstract: A semiconductor package is provided. A leadframe including a die attach paddle, a number of inner leads, and a number of outer leads, and a number of extended lead tips on the number of outer leads. The inner edges of the number of extended lead tips are in substantial alignment with the inner edges of the number of inner leads. A die is attached to the die attach paddle. A number of bonding wires is used to connect the die to the number of inner leads and the extended lead tips on the number of outer leads, and an encapsulant is formed over the leadframe and the die.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: June 13, 2006
    Assignee: St Assembly Test Services Ltd.
    Inventors: Jeffrey D. Punzalan, Jose Alvin Caparas, Jae Hun Ku
  • Patent number: 7008820
    Abstract: A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are formed between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: March 7, 2006
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, Jr.
  • Patent number: 7005325
    Abstract: A system is provided for an integrated circuit package including a leadframe having a lead finger. A groove is formed in a lead finger for a conductive bonding agent and a passive device is placed in the groove to be held by the conductive bonding agent.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: February 28, 2006
    Assignee: St Assembly Test Services Ltd.
    Inventors: Seng Guan Chow, Il Kwon Shim, Ming Ying, Byung Hoon Ahn
  • Patent number: 7005370
    Abstract: A method for manufacturing an integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is formed over the substrate. A second metallurgy layer is formed over the first metallurgy layer. The first metallurgy layer is removed while leaving a portion thereof over the second contact pad. The second metallurgy layer is removed while leaving a portion thereof over the second contact pad. A protective layer is formed over the first contact pad while removing the first metallurgy layer.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: February 28, 2006
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Lun Zhao, Wan Lay Looi, Kyaw Oo Aung, Yonggang Jin, Jae-Yong Song, Won Sun Shin
  • Publication number: 20060012022
    Abstract: An integrated circuit die is provided having a body portion having a singulation side and a pedestal portion extending from the body portion and having a singulation side coplanar with the singulation side of the body portion.
    Type: Application
    Filed: July 19, 2004
    Publication date: January 19, 2006
    Applicant: ST Assembly Test Services Ltd.
    Inventors: Virgil Ararao, Il Shim, Seng Chow
  • Patent number: 6979907
    Abstract: An integrated circuit package is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: December 27, 2005
    Assignee: St Assembly Test Services Ltd.
    Inventors: Jian Jun Li, Il Kwon Shim, Guruprasad Badakere
  • Publication number: 20050277227
    Abstract: A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are formed between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
    Type: Application
    Filed: June 10, 2004
    Publication date: December 15, 2005
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Il Shim, Kwee Tan, Jian Li, Dario Filoteo
  • Publication number: 20050260787
    Abstract: A semiconductor package is provided. A leadframe including a die attach paddle, a number of inner leads, and a number of outer leads, and a number of extended lead tips on the number of outer leads. The inner edges of the number of extended lead tips are in substantial alignment with the inner edges of the number of inner leads. A die is attached to the die attach paddle. A number of bonding wires is used to connect the die to the number of inner leads and the extended lead tips on the number of outer leads, and an encapsulant is formed over the leadframe and the die.
    Type: Application
    Filed: May 13, 2004
    Publication date: November 24, 2005
    Applicant: ST ASSEMBLY TEST SERVICES
    Inventors: Jeffrey Punzalan, Jose Caparas, Jae Ku