Patents Assigned to ST Assembly Test Services
  • Publication number: 20040262718
    Abstract: A semiconductor package and a method of assembly therefor are provided. A semiconductor package has a die pad and a plurality of bonding fingers. A spacer is attached to the die pad, and a large die is attached to the spacer. The large die is wire bonded to the plurality of bonding fingers using a plurality of bonding wires. The die pad, plurality of bonding fingers, spacer, large die, and bonding wires are encapsulated to form the semiconductor package. The semiconductor package can be either a single or dual row package, such as a QFN or BGA package.
    Type: Application
    Filed: June 25, 2003
    Publication date: December 30, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventor: Kambhampati Ramakrishna
  • Patent number: 6834658
    Abstract: An apparatus is provided to clean melamine deposits from tools and components that are used to form molds around and to therewith encapsulate BGA devices. The cleaning apparatus uses a dummy BGA substrate as part of and during the cleaning procedure. This dummy BGA substrate replaces the conventionally used copper strips that shield areas of the molding tools during the cleaning cycle. The dummy copper strips require, during and as part of the melamine cleaning process, frequent cleaning, which adds considerably to the time and expense of the melamine cleaning process.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: December 28, 2004
    Assignee: St Assembly Test Services PTE Ltd.
    Inventor: Loreto Ycong Cantillep
  • Patent number: 6833287
    Abstract: A semiconductor package with stacked dies and method of assembly is provided. A first die is attached to a substrate. A protective layer is placed on the first die over a central area thereof. The first die is electrically connected to the substrate. An intermediate adhesive layer is applied over the protective layer. A second die is attached to the intermediate adhesive layer and electrically connected to the substrate.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: December 21, 2004
    Assignee: ST Assembly Test Services Inc.
    Inventors: Hyeong Ryeol Hur, Henry D. Bathan, Zigmund R. Camacho
  • Publication number: 20040253763
    Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.
    Type: Application
    Filed: May 19, 2004
    Publication date: December 16, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Jeffrey D. Punzalan, Jae Hun Ku, Byung Joon Han
  • Publication number: 20040251526
    Abstract: A semiconductor package with stacked dies and method of assembly is provided. A first die is attached to a substrate. A protective layer is placed on the first die over a central area thereof. The first die is electrically connected to the substrate. An intermediate adhesive layer is applied over the protective layer. A second die is attached to the intermediate adhesive layer and electrically connected to the substrate.
    Type: Application
    Filed: June 16, 2003
    Publication date: December 16, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Hyeong Ryeol Hur, Henry D. Bathan, Zigmund R. Camacho
  • Patent number: 6828671
    Abstract: A new method is provided for the establishment of a low resistivity connection between a wire bonded IC chip that is mounted on a heatsink and the heatsink of the package. A copper trace connection is allocated for this purpose on the surface of the substrate layer to which the IC chip is connected. An opening is provided in the substrate layer of the package, this opening aligns with the copper trace that has been allocated for establishing a ground connection and penetrates the substrate layer down to the surface of the underlying heatsink. The opening is filled with a conductive epoxy or an equivalent low-resistivity material thereby establishing a direct electrical connection or short between the allocated copper trace and the underlying heatsink. By connecting the ground point of the IC chip to the allocated copper trace, a direct electrical low resistivity connection is made between the ground point of the IC chip and the heatsink into which the IC chip is mounted.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: December 7, 2004
    Assignee: ST Assembly Test Services PTE LTD
    Inventors: Weddie Aquien, John Briar, Setho Sing Fee
  • Patent number: 6825067
    Abstract: A new method is provided for the creation of a mold cap. The mold cap anchoring feature of the invention is designed and incorporated from the start of the design and fabrication of the substrate. Various design options of the mold anchor of the invention can be implemented. The mold anchor of the invention allows the mold compound to flow underneath the substrate where the mold compound will remain in place until the process of mold formation is completed. The mold compound of the package will penetrate all available cavities surrounding and being accessible from the mold anchor of the invention where the mold compound will remain in place and harden. After hardening, the mold compound surrounding the mold anchor will support the anchored area.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: November 30, 2004
    Assignee: St Assembly Test Services PTE LTD
    Inventors: Virgil C. Ararao, Hermes T. Apale, Il Kwon Shim
  • Patent number: 6818981
    Abstract: A PBGA package is provided. The heat spreader interfaces with the substrate with the standoff of the heat spreader. The stand-off of the heat spreader is provided with an opening, the stand-off of the heat spreader is aligned with the substrate of the PBGA package by means of a copper pad that is provided over a second surface of the substrate. A solder bump is further provided over the surface of the copper pad. Thermally conductive solder is deposited over the opening of the heat spreader and over the copper pad. If the heat spreader stand-off is aligned with contact pads, thermally conductive epoxy is deposited over the contact pads.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: November 16, 2004
    Assignee: St Assembly Test Services PTE LTD
    Inventors: Il Kwon Shim, Hermes T. Apale, Gerry Balanon
  • Publication number: 20040211817
    Abstract: A system is provided for reflow soldering a part that includes: replacing air around an unsoldered part with a first inert gas; removing the first inert gas to form a vacuum around the unsoldered part; vacuum reflow soldering the unsoldered part to form a reflow-soldered part; providing a second inert gas to fill the vacuum around the reflow-soldered part; and replacing the second inert gas with air around the reflow-soldered part.
    Type: Application
    Filed: April 16, 2004
    Publication date: October 28, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Yonggang Jin, Shelley Yong, Puay Gek Chua, Won Sun Shin
  • Patent number: 6802445
    Abstract: A new method is provided for the creation of high-accuracy and low-accuracy openings overlying points of electrical access over the surface of a semiconductor device supporting substrate. Openings are first created for access to the substrate followed by copper plating and then patterning of the plated layer of copper, creating the interconnect metal over the surface of the substrate. A first solder mask is coated over the surface of the substrate, this first solder mask must be provided with a first array of low-accuracy openings for electrical access there-through for the placement of contact balls. The first openings can be created using conventional film artwork since low accuracy is required for the contact ball openings, resulting in a low-cost process for the creation of the first openings. A second solder mask is next coated over the surface of the first solder mask.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: October 12, 2004
    Assignee: St Assembly Test Services Pte. Ltd.
    Inventors: Il Kwon Shim, Jian Jun Li, Sheila Marie Alvarez
  • Publication number: 20040180525
    Abstract: A new method and assembly is provided for anchoring the heat spreader of a PBGA package to the substrate thereof. Anchor features are made part of the PBGA package, these anchor features are provided over the surface of the substrate of the PBGA package. The anchor features align with openings created in the heat spreader stand-off, thus allowing for quick and reliable positioning and anchoring of the heat spreader over the surface of the substrate of the package.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 16, 2004
    Applicant: ST Assembly Test Services Ltd.
    Inventors: Il Kwon Shim, Hermes T. Apale, Weddie Aquien, Dario Filoteo, Virgil Ararao, Leo Merilo
  • Publication number: 20040178503
    Abstract: A new method and sequence is provided for the creation of solder bumps. The design of the invention implements a torch bump, which is a solder bump comprising a base over which a solder bump is created. A first layer of dry film is laminated over a supporting surface over which first a layer of UBM has been deposited. A base for the solder bump is created in a first opening created through the first layer of dry film, the created base aligns with an underlying contact pad. A second dry film is laminated over the surface of the first dry film, a second opening is created through the second dry film that aligns with the created base of the solder bump. The opening through the second dry film is filled with solder by solder printing, the first and second layers of dry film are removed, the deposited layer of UBM is etched.
    Type: Application
    Filed: March 1, 2004
    Publication date: September 16, 2004
    Applicant: ST Assembly Test Services Pte Ltd
    Inventors: Yong Gang Jin, Won Sun Shin
  • Patent number: 6791346
    Abstract: A method and apparatus for handling small semiconductor devices in the testing of these devices. Multiple devices are mounted within a device strip carrier and are positioned in the testing position. This positioning of the device strip carriers is performed using device strip carrier alignment tools; the device strip carrier can readily be repositioned with respect to the test head/probe card for testing of multiple devices contained within the device strip carrier.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: September 14, 2004
    Assignee: St. Assembly Test Services Pte Ltd
    Inventors: Rajiv Mehta, Liop-Jin Yap, Raymundo M. Camenforte, Chee-Keong Tan
  • Patent number: 6775140
    Abstract: A method for fabricating a semiconductor device heat spreader from a unitary piece of metallic material. The metallic material is stamped to form a unitary heat spreader having an upper heat dissipation region, a lower substrate contact region, and supports connecting the upper heat dissipation region and the lower substrate contact region. A recess is formed within the supports and the upper and lower regions for receiving a semiconductor device.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: August 10, 2004
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Virgil Cotoco Ararao, Sheila Marie L. Alvarez, Roger Emigh
  • Patent number: 6774640
    Abstract: A new method is provided for evaluating the alignment of inner layers of interconnect layers. A test pattern is inserted within and as part of the process of creating a saw singulated plastic ball grid array substrate. The test pattern comprises a test point of reference for each inner layer of the substrate and multiple measurement points relating to the point of reference whereby each of these multiple measurement points is indicative of an amount of clearance or misalignment with respect to that inner-layer. By measuring electrical continuity or lack thereof between the point of reference and the respective multiple measurement points relating to the point of reference and by identifying which of the multiple points is shorted to the point of reference, the mis-alignment of the inner layers of the saw singulated plastic ball grid array substrate can be determined.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: August 10, 2004
    Assignee: St Assembly Test Services Pte Ltd.
    Inventor: Jian-Jun Li
  • Patent number: 6770962
    Abstract: A substrate and method of encapsulating a substrate based electronic package using injection molding and a two piece mold is described. The substrate has a barrier material formed on a gating region of the substrate. The barrier material can be formed directly over circuit wiring traces formed on the substrate thereby avoiding restrictions on the location of circuit wiring traces. The barrier material and encapsulant are chosen such that the adhesive force between the barrier material and the encapsulant is greater than the adhesive force between the barrier material and the substrate. When the mold runner is broken away the barrier material is also peeled away without damage to the substrate or circuit wiring traces.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: August 3, 2004
    Assignee: St Assembly Test Services Ltd.
    Inventor: John Briar
  • Publication number: 20040145039
    Abstract: A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is then mounted on the interposer.
    Type: Application
    Filed: September 30, 2003
    Publication date: July 29, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow, Byung Joon Han
  • Publication number: 20040134054
    Abstract: The present invention provides a kit and method for package-to-package conversion of a pick and place handler. An input arm assembly is provided with interchangeable vacuum leads such that package-to-package conversion only requires replacing the vacuum lead with a different size vacuum lead. An input/output shuttle plate is provided comprising a block and base plate. The block has a plurality of pocket groupings and a two or more alignment hole groupings. The base plate has two or more alignment pins. Package-to-package conversion is achieved by changing which alignment hole in each alignment hole grouping is set on the alignment pins, thereby selecting the pocket in each pocket grouping corresponding to the alignment hole used. A soak plate is provided having an array of pocket groupings, wherein each pocket grouping has the same pattern of different size/shape pockets to accommodate different packages.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 15, 2004
    Applicant: ST ASSEMBLY TEST SERVICES PTE LTD
    Inventors: Kai Wah Sum, Wee Boon Tan, Liop Jin Yap
  • Patent number: 6759752
    Abstract: A package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: July 6, 2004
    Assignee: St Assembly Test Services Ltd.
    Inventors: Raymundo M. Camenforte, John Briar
  • Patent number: 6750534
    Abstract: A new method is provided to identify semiconductor devices whereby the invention provides for a shallow depression on the backside of the heat sink of the ball grid array package. This shallow depression or hole can be used for visual and optical inspection of the device orientation.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: June 15, 2004
    Assignee: ST Assembly Test Services Ltd
    Inventors: Weddie Pacio Aquien, Loreto Y. Cantillep, Setho Sing Fee