Patents Assigned to ST Assembly Test Services
  • Publication number: 20040108601
    Abstract: A new method is provided for the creation of a mold cap. The mold cap anchoring feature of the invention is designed and incorporated from the start of the design and fabrication of the substrate. Various design options of the mold anchor of the invention can be implemented. The mold anchor of the invention allows the mold compound to flow underneath the substrate where the mold compound will remain in place until the process of mold formation is completed. The mold compound of the package will penetrate all available cavities surrounding and being accessible from the mold anchor of the invention where the mold compound will remain in place and harden. After hardening, the mold compound surrounding the mold anchor will support the anchored area.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 10, 2004
    Applicant: St Assembly Test Services Pte Ltd
    Inventors: Virgil C. Ararao, Hermes T. Apale, Il Kwon Shim
  • Patent number: 6744125
    Abstract: A new method and package is provided for the packaging of semiconductor devices. The method and package starts with a semiconductor substrate, the substrate is pre-baked. In the first embodiment of the invention, a copper foil is attached to the substrate, in the second embodiment of the invention a adhesive film is attached to the substrate. Processing then continues by attaching the die to the copper foil under the first embodiment of the invention and to the film under the second embodiment of the invention. After this the processing continues identically for the two embodiments of the invention with steps of curing, plasma cleaning, wire bonding, optical inspection, plasma cleaning and providing a molding around the die and the wires connected to the die. For the second embodiment of the invention, the film is now detached and replaced with a copper foil.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: June 1, 2004
    Assignee: St. Assembly Test Services Ltd.
    Inventors: Raymundo M. Camenforte, Dioscoro A. Merilo, Seng Guan Chow
  • Patent number: 6740577
    Abstract: A torch bump is provided, which is a solder bump comprising a base over which a solder bump is created. A first layer of dry film is over a supporting surface over which first a layer of UBM has been deposited. A base for the solder bump is created in a first opening through the first layer of dry film, the base aligns with an underlying contact pad. A second dry film is over the surface of the first dry film, a second opening is created through the second dry film that aligns with the created base of the solder bump. The opening through the second dry film is filled with solder by solder printing, the first and second layers of dry film are removed, the deposited layer of UBM is etched. Reflow is applied to the deposited solder, creating the torch solder.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: May 25, 2004
    Assignee: St Assembly Test Services Pte LTD
    Inventors: Yong Gang Jin, Won Sun Shin
  • Patent number: 6737298
    Abstract: A new method and assembly are provided for anchoring the heat spreader of a PBGA package to the substrate thereof. Anchor features are made part of the PBGA package. These anchor features are provided over the surface of the substrate of the PBGA package. The anchor features align with openings created in the heat spreader stand-off, thus allowing for quick and reliable positioning and anchoring of the heat spreader over the surface of the substrate of the package.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: May 18, 2004
    Assignee: St Assembly Test Services Ltd
    Inventors: Il Kwon Shim, Hermes T. Apale, Weddle Aquien, Dario Filoteo, Virgil Ararao, Leo Merilo
  • Publication number: 20040079788
    Abstract: A new method is provided for the creation of high-accuracy and low-accuracy openings overlying points of electrical access over the surface of a semiconductor device supporting substrate. Openings are first created for access to the substrate followed by copper plating and then patterning of the plated layer of copper, creating the interconnect metal over the surface of the substrate. A first solder mask is coated over the surface of the substrate, this first solder mask must be provided with a first array of low-accuracy openings for electrical access there-through for the placement of contact balls. The first openings can be created using conventional film artwork since low accuracy is required for the contact ball openings, resulting in a low-cost process for the creation of the first openings. A second solder mask is next coated over the surface of the first solder mask.
    Type: Application
    Filed: October 24, 2002
    Publication date: April 29, 2004
    Applicant: St Assembly Test Services Pte Ltd
    Inventors: Il Kwon Shim, Jian Jun Li, Sheila Marie Alvarez
  • Publication number: 20040075987
    Abstract: A method for fabricating a semiconductor device heat spreader from a unitary piece of metallic material. The metallic material is stamped to form a unitary heat spreader having an upper heat dissipation region, a lower substrate contact region, and supports connecting the upper heat dissipation region and the lower substrate contact region. A recess is formed within the supports and the upper and lower regions for receiving a semiconductor device.
    Type: Application
    Filed: May 7, 2003
    Publication date: April 22, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Il Kwon Shim, Seng Guan Chow, Virgil Cotoco Ararao, Sheila Marie L. Alvarez, Roger Emigh
  • Publication number: 20040070055
    Abstract: A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.
    Type: Application
    Filed: June 16, 2003
    Publication date: April 15, 2004
    Applicant: ST ASSEMBLY TEST SERVICES PTE LTD
    Inventors: Jeffrey D. Punzalan, Hien Boon Tan, Zheng Zheng, Jae Hak Yee, Byung Joon Han
  • Patent number: 6718608
    Abstract: A method is provided for package-to-package conversion of a pick and place handler. An input arm assembly is provided with interchangeable vacuum leads. An input/output shuttle plate is provided comprising a block and base plate. The block has a plurality of pocket groupings and a two or more alignment hole groupings. The base plate has two or more alignment pins. Package-to-package conversion is achieved by changing alignment hole groupings on the alignment pins, thereby selecting the pocket corresponding to the alignment hole used. A soak plate is provided having an array of pocket groupings, wherein each pocket grouping has the same pattern of different size/shape pockets to accommodate different packages. Package-to-package conversion is accomplished by programming an offset to the desired pocket in each pocket grouping. A test arm assembly is provided with interchangeable vacuum leads and interchangeable nest pieces.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: April 13, 2004
    Assignee: St Assembly Test Services Pte LTD
    Inventors: Sum Kai Wah, Tan Wee Boon, Yap Liop Jin
  • Publication number: 20040061202
    Abstract: A leadframe design (and method of forming the leadframe design), comprising: an inner die pad structure lying in a first plane; and an outer die pad structure supported by outer tie bars and connected to the inner die pad by inner tie bars. The outer die pad structure lying in a second plane spaced apart from the inner die pad structure first plane. An outer package surrounds at least the inner die pad structure and the inner tie bars. The outer die pad structure being supported by the outer tie bars. The outer package having outer walls. Lead fingers extend through the outer package outer walls and include respective inner portions extending into the outer package proximate the inner and outer die pad structures.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Applicant: St Assembly Test Services Pte Ltd
    Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow
  • Publication number: 20040061204
    Abstract: A leadframe for a semiconductor package includes signal and ground leads, a ground plane, and a frame paddle. Supports connect the signal and ground leads, ground plane, and frame paddle in at least two different layers. At least one force release and stress relief structure is incorporated into the leadframe to free the ground plane substantially from distortion and warpage resulting from residual mechanical stresses therein.
    Type: Application
    Filed: May 23, 2003
    Publication date: April 1, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Byung Joon Han, Byung Hoon Ahn, Zheng Zheng
  • Publication number: 20040061205
    Abstract: A leadframe for a semiconductor die includes signal leads, ground leads, and a die support holder for supporting the semiconductor die. The die support holder has opposite surfaces and side edges therebetween. The opposite die support holder surfaces are smaller in transverse extent than the semiconductor die for supporting the die on one of the opposite die support holder surfaces such that the die extends beyond the side edges of the die support holder.
    Type: Application
    Filed: May 23, 2003
    Publication date: April 1, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Byung Joon Han, Byung Hoon Ahn
  • Patent number: 6710438
    Abstract: A chip scale package assembly comprises an integrated circuit die wire bonded to a carrier for mounting to a printed circuit board. The carrier comprises top and bottom ground planes thermally and electrically bonded together by a number of grounded thermal vias. The top ground plane completely surrounds the wire bond signal connections made with the die, enhancing signal integrity. The top ground plane covers the die mounting area, providing grounding and heat spreading for the die. The thermal vias are also positioned in the mounting area, and thermally couple the die to the bottom-side ground plane. The bottom ground plane is positioned within a central area around which the signal connections from the top-side are arranged. Ground pads with attached solder balls are positioned within the bottom ground plane and conduct heat transferred from the die into a primary circuit board on which the carrier is mounted.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: March 23, 2004
    Assignees: Institute of Microelectronics, Advanced Micro Devices (s) PTE LTD, Agilent Technologies Singapore PTE LTD, Amkor Technology Inc., Delphi Automotive Systems Singapore PTE LTD, Infineon Technologies (Asia Pacific) PTE LTD, Agere Systems Singapore PTE LTD, Motorola Electronics PTE LTD, Philips Electronics Singapore PTE LTD, St Assembly Test Services PTE LTD
    Inventors: Yong Kee Yeo, Navas O.K. Khan, Mahadevan K. Iyer
  • Patent number: 6706563
    Abstract: A new method is provided for the interface between a heat spreader and the substrate of a thermally improved PBGA package. The heat spreader interfaces with the substrate with the standoff of the heat spreader. The stand-off of the heat spreader is provided with an opening, the stand-off of the heat spreader is aligned with the substrate of the PBGA package by means of a copper pad that is provided over a second surface of the substrate. A gold stud bump or a solder bump are further provided over the surface of the copper pad for alignment purposes. Thermally conductive epoxy or solder is deposited over the opening of the heat spreader and therewith over the copper pad provided over a second surface of the substrate.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: March 16, 2004
    Assignee: ST Assembly Test Services PTE LTD
    Inventors: Il Kwon Shim, Hermes T. Apale, Gerry Balanon
  • Publication number: 20040036068
    Abstract: A new method is provided for evaluating the alignment of inner layers of interconnect layers. A test pattern is inserted within and as part of the process of creating a saw singulated plastic ball grid array substrate. The test pattern comprises a test point of reference for each inner layer of the substrate and multiple measurement points relating to the point of reference whereby each of these multiple measurement points is indicative of an amount of clearance or misalignment with respect to that inner-layer. By measuring electrical continuity or lack thereof between the point of reference and the respective multiple measurement points relating to the point of reference and by identifying which of the multiple points is shorted to the point of reference, the mis-alignment of the inner layers of the saw singulated plastic ball grid array substrate can be determined.
    Type: Application
    Filed: August 20, 2002
    Publication date: February 26, 2004
    Applicant: St Assembly Test Services Pte Ltd
    Inventor: Jian-Jun Li
  • Patent number: 6686258
    Abstract: When leaded semiconductor packages are formed, semiconductor dies are mounted onto lead frames of a panel, via adhesive tape to be later removed. Such frames are arranged in plural snips. Each frame has plural leads, which are formed when the panel is punched and which are singulated when such strips are sawn across.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: February 3, 2004
    Assignee: ST Assembly Test Services Ltd.
    Inventor: Jae Hak Yee
  • Patent number: 6660565
    Abstract: In accordance with the objectives of the invention a new method is provided to insert the underfill for flip-chip semiconductor devices. An IC chip is provided with solder bumps. The flip-chip is entered into an enclosed space, the heatsink forms the top of the enclosed space, the substrate forms the bottom of the enclosed space. The enclosed space is filled with a mold compound. This mold compound now surrounds the IC chip thereby including the area below the IC. The step of inserting the underfill as a separate processing step has thereby been eliminated.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: December 9, 2003
    Assignee: St Assembly Test Services Pte Ltd.
    Inventor: John Briar
  • Publication number: 20030219966
    Abstract: A new method and sequence is provided for the creation of solder bumps. The design of the invention implements a torch bump, which is a solder bump comprising a base over which a solder bump is created. A first layer of dry film is laminated over a supporting surface over which first a layer of UBM has been deposited. A base for the solder bump is created in a first opening created through the first layer of dry film, the created base aligns with an underlying contact pad. A second dry film is laminated over the surface of the first dry film, a second opening is created through the second dry film that aligns with the created base of the solder bump. The opening through the second dry film is filled with solder by solder printing, the first and second layers of dry film are removed, the deposited layer of UBM is etched.
    Type: Application
    Filed: May 21, 2002
    Publication date: November 27, 2003
    Applicant: St Assembly Test Services Pte Ltd
    Inventors: Yong Gang Jin, Won Sun Shin
  • Publication number: 20030216024
    Abstract: In accordance with the objectives of the invention a new method is provided to position and secure a heat sink over the surface of a semiconductor device mounting support, the latter typically being referred to as a semiconductor substrate. A plurality of recesses is created in the surface of the substrate over which the heat sink is to be mounted. The heat sink is (conventionally and not part of the invention) provided with dimples that form the interface between the heat sink and the underlying substrate. The dimples of the heat sink are aligned with and inserted into the recesses that have been created by the invention in the underlying substrate for this purpose, firmly securing the heat sink in position with respect to the substrate.
    Type: Application
    Filed: June 16, 2003
    Publication date: November 20, 2003
    Applicant: ST ASSEMBLY TEST SERVICES PTE LTD
    Inventors: Il Kwon Shim, Seng Guan Chow, Gerry Balanon
  • Publication number: 20030197195
    Abstract: A new method is provided for the interface between a heat spreader and the substrate of a thermally improved PBGA package. The heat spreader interfaces with the substrate with the standoff of the heat spreader. The stand-off of the heat spreader is provided with an opening, the stand-off of the heat spreader is aligned with the substrate of the PBGA package by means of a copper pad that is provided over a second surface of the substrate. A gold stud bump or a solder bump are further provided over the surface of the copper pad for alignment purposes. Thermally conductive epoxy or solder is deposited over the opening of the heat spreader and therewith over the copper pad provided over a second surface of the substrate.
    Type: Application
    Filed: April 10, 2002
    Publication date: October 23, 2003
    Applicant: St Assembly Test Services Pte Ltd
    Inventors: Il Kwon Shim, Hermes T. Apale, Gerry Balanon
  • Patent number: 6630373
    Abstract: A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: October 7, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Jeffrey D. Punzalan, Hien Boon Tan, Zheng Zheng, Jae Hak Yee, Byung Joon Han