Abstract: A method for manufacturng an integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is formed over the substrate. A second metallurgy layer is formed over the first metallurgy layer. The first metallurgy layer is removed while leaving a portion thereof over the second contact pad. The second metallurgy layer is removed while leaving a portion thereof over the second contact pad. A protective layer is formed over the first contact pad while removing the first metallurgy layer.
Type:
Application
Filed:
May 13, 2004
Publication date:
November 17, 2005
Applicant:
ST ASSEMBLY TEST SERVICES LTD.
Inventors:
Lun Zhao, Wan Looi, Kyaw Aung, Yonggang Jin, Jae-Yong Song, Won Shin
Abstract: A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of the leadfingers.
Abstract: An electronic device having a substrate carrier is provided. A semiconductor connected to the substrate carrier. A heat spreader having upper and lower surfaces and legs recessed below the lower surface is connected to the substrate carrier. The Z-dimension between the heat spreader and the substrate carrier is maintained over substantially the entire area of the substrate carrier.
Type:
Application
Filed:
April 30, 2004
Publication date:
November 3, 2005
Applicant:
ST Assembly Test Services Ltd.
Inventors:
Il Shim, Sheila Marie Alvarez, Virgil Ararao
Abstract: An embodiment of the present invention allows mold compound to flow underneath a substrate where the mold compound will remain in place until the process of mold formation is completed. The mold compound of the package will penetrate all available cavities where the mold compound will remain in place and harden. After hardening, the mold compound surrounding a mold anchor will support an anchored area.
Type:
Grant
Filed:
August 9, 2004
Date of Patent:
November 1, 2005
Assignee:
ST Assembly Test Services, LTD
Inventors:
Virgil C. Ararao, Hermes T. Apale, Il Kwon Shim
Abstract: A substrate is provided. A first die is attached to the substrate. The first die is electrically connected to the substrate. A heat sink having an undercut around its periphery is attached to the first die. A second die is attached to the heat sink. The second die is electrically connected to the substrate, and the first die, the heat sink, and the second die are encapsulated.
Abstract: An integrated circuit package is provided with a connective structure having a wire bonding zone and a keep-out zone. An integrated circuit die has an undercut defining an undercut zone, which is overlapped by the keep-out zone. A wire is bonded between the integrated circuit die and the connective structure within the wire bonding zone and outside of the keep-out zone.
Type:
Application
Filed:
March 3, 2004
Publication date:
September 8, 2005
Applicant:
ST Assembly Test Service Ltd.
Inventors:
Il Kwon Shim, Virgil Ararao, Hyeong Hur, Byung Han
Abstract: A system is provided for an integrated circuit package including a leadframe having a lead finger. A groove is formed in a lead finger for a conductive bonding agent and a passive device is placed in the groove to be held by the conductive bonding agent.
Type:
Application
Filed:
February 5, 2004
Publication date:
August 11, 2005
Applicant:
ST ASSEMBLY TEST SERVICES LTD.
Inventors:
Seng Chow, Il Shim, Ming Ying, Byung Ahn
Abstract: A semiconductor package and a method of assembly therefor are provided. A semiconductor package has a die pad and a plurality of bonding fingers. A spacer is attached to the die pad, and a large die is attached to the spacer. The large die is wire bonded to the plurality of bonding fingers using a plurality of bonding wires. The die pad, plurality of bonding fingers, spacer, large die, and bonding wires are encapsulated to form the semiconductor package. The semiconductor package can be either a single or dual row package, such as a QFN or BGA package.
Abstract: A method for fabricating a semiconductor package with a substrate in a strip format is provided. Semiconductor devices are attached in a strip format to the substrate, and a thermal interface material is applied to the semiconductor devices. A flat panel heat spreader is attached to each semiconductor device. The semiconductor devices are encapsulated with open encapsulation, leaving the surface of the flat panel heat spreader opposite the substrate externally exposed. Individual semiconductor packages are then singulated from the strip format.
Type:
Application
Filed:
January 27, 2004
Publication date:
July 28, 2005
Applicant:
ST ASSEMBLY TEST SERVICES LTD.
Inventors:
Tie Wang, Virgil Ararao, Il Shim, Sheila Marie Alvarez
Abstract: Semiconductor packages provide a leadframe for packages that are singulated with respective predetermined package body sizes. Individual mold caps are formed on the leadframe with mold cap dimensions that are larger than the respective predetermined package body sizes. The mold caps and leadframe are singulated to the respective predetermined package body sizes.
Abstract: A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is mounted on the interposer.
Type:
Application
Filed:
November 10, 2004
Publication date:
April 28, 2005
Applicant:
ST ASSEMBLY TEST SERVICES LTD.
Inventors:
Il Shim, Kambhampati Ramakrishna, Seng Chow, Byung Han
Abstract: A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.
Type:
Grant
Filed:
June 16, 2003
Date of Patent:
April 5, 2005
Assignee:
ST Assembly Test Services Pte Ltd.
Inventors:
Jefferey D. Punzalan, Hien Boon Tan, Zheng Zheng, Jae Hak Yee, Byung Joon Han
Abstract: A method and assembly are provided for anchoring the heat spreader of a PBGA package to the substrate thereof as part of the PBGA package. These anchor features are provided over the surface of the substrate of the PBGA package. The anchor features align with openings created in the heat spreader stand-off, thus allowing for quick and reliable positioning and anchoring of the heat spreader over the surface of the substrate of the package.
Type:
Grant
Filed:
March 18, 2004
Date of Patent:
April 5, 2005
Assignee:
ST Assembly Test Services PTE LTD
Inventors:
Il Kwon Shim, Hermes T. Apale, Weddie Aquien, Dario Filoteo, Virgil Ararao, Leo Merilo
Abstract: An integrated circuit package is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
Abstract: A method for forming a heat spreader, and the heat spreader formed thereby, are disclosed. An array heat spreader having a plurality of connected heat spreader panels is formed. Slots are formed in opposing sides of the heat spreader panels. Legs are formed on and extending downwardly from each of the heat spreader panels in at least an opposing pair of the slots on the heat spreader panels. The legs are integral with the respective heat spreader panels from which they depend.
Type:
Application
Filed:
August 18, 2004
Publication date:
March 3, 2005
Applicant:
ST Assembly Test Services Ltd.
Inventors:
Il Shim, Kambhampati Ramakrishna, Diane Sahakian, Seng Chow, Dario Filoteo, Virgil Ararao
Abstract: A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is then mounted on the interposer.
Type:
Grant
Filed:
September 30, 2003
Date of Patent:
March 1, 2005
Assignee:
ST Assembly Test Services, Ltd.
Inventors:
Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow, Byung Joon Han
Abstract: A method for fabricating semiconductor packages provides a leadframe for packages that are to be singulated with respective predetermined package body sizes. Individual mold caps are formed on the leadframe with mold cap dimensions that are larger than the respective predetermined package body sizes. The mold caps and leadframe are sawed to singulate packages therefrom. The sawing reduces the dimensions of the mold caps to the respective predetermined package body sizes.
Abstract: An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
Type:
Grant
Filed:
September 19, 2002
Date of Patent:
February 15, 2005
Assignee:
St Assembly Test Services Ltd.
Inventors:
Jian Jun Li, Il Kwon Shim, Guruprasad Badakere
Abstract: An embodiment of the present invention allows mold compound to flow underneath a substrate where the mold compound will remain in place until the process of mold formation is completed. The mold compound of the package will penetrate all available cavities where the mold compound will remain in place and harden. After hardening, the mold compound surrounding a mold anchor will support an anchored area.
Abstract: A leadframe design (and method of forming the leadframe design), comprising: an inner die pad structure lying in a first plane; and an outer die pad structure supported by outer tie bars and connected to the inner die pad by inner tie bars. The outer die pad structure lying in a second plane spaced apart from the inner die pad structure first plane. An outer package surrounds at least the inner die pad structure and the inner tie bars. The outer die pad structure being supported by the outer tie bars. The outer package having outer walls. Lead fingers extend through the outer package outer walls and include respective inner portions extending into the outer package proximate the inner and outer die pad structures.
Type:
Grant
Filed:
September 27, 2002
Date of Patent:
January 11, 2005
Assignee:
ST Assembly Test Services PTE Ltd.
Inventors:
Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow