Abstract: Disclosed herein is a method of making a microelectromechanical (MEMS) device. The method includes, in a single structural layer, affixing a tiltable structure to an anchorage portion with first and second supporting arms extending between the anchorage portion and opposite sides of the tiltable structure, and forming first and second resonant piezoelectric actuation structures extending between a constraint portion of the first supporting arm and the anchorage portion, on opposite sides of the first supporting arm. The method further includes coupling a handling wafer underneath the structural layer to define a cavity therebetween, and forming a passivation layer over the structural layer, the passivation layer having contact openings defined therein for routing metal regions for electrical coupling to respective electrical contact pads, the electrical contact pads being electrically connected to the first and second resonant piezoelectric actuation structures.

Abstract: Signal processing is applied to a digital audio input signal to provide an analog audio output signal using a switching converter circuit driven by a pulse-width-modulated (PWM) signal. The analog audio output signal is sensed to provide an analog feedback signal. The signal processing that is applied includes: converting the digital audio input signal to producing an analog replica; producing an analog error signal indicative of a difference between the analog replica of the digital input signal and the analog feedback signal; converting the analog error signal to produce a digital error signal; digitally filtering the digital error signal to produce a filtered digital error signal; and generating the PWM signal from the filtered digital error signal.

Abstract: An earphone device has a casing having a measurement portion dedicated to acquisition of at least one measurement quantity with the earphone device arranged outside an ear of a subject. The earphone device is provided with at least one sensor, operatively coupled to the measurement portion within the casing for acquiring signals indicative of the measurement quantity, and a processing module that processes the signals acquired by the sensor so as to provide a processed output signal for monitoring the measurement quantity, as a function of the acquired signals. Electrical-connection elements define electrical paths within the casing in electrical connection with the sensor.

Abstract: A signal decode circuit is coupled to a buffer for each signal channel. A memory includes a shared area configured to store waveform data sets, each waveform data set including a sequence of coded waveform values specifying waveform step states. The shared area further stores delay data sets, each delay data set including a digital delay value for each signal channel defining a delay profile. A signal pointer addresses the shared area to read one waveform data set from the memory with the sequence of coded waveform values being selectively loaded into one or more of the buffers. A delay pointer addresses the shared area to read one delay data set from the memory with the digital delay values used to control delayed actuation of the signal decode circuits to decode the sequence of coded waveform values from the buffers and generate waveform signals in accordance with the delay profile.

Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.

Abstract: In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. A selection line for each one of the slave devices couples the master device with a respective slave device and is dedicated to selection by the master device of the respective slave device for communication over the shared data communication bus. Each of the slave devices is able to send an interrupt request to the master device over the respective selection line to be served by the master device initiating a communication over the shared data communication bus, each selection line thereby being a bidirectional communication line between the respective slave device and the master device.

Abstract: Electronic device comprising: a semiconductor body, in particular of Silicon Carbide, SiC, having a first and a second face, opposite to each other along a first direction; and an electrical terminal at the first face, insulated from the semiconductor body by an electrical insulation region. The electrical insulation region is a multilayer comprising: a first insulating layer, of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer on the first insulating layer, of a Hafnium Oxide; and a third insulating layer on the second insulating layer, of an Aluminum Oxide.

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

Abstract: In accordance with an embodiment, a circuit is configured to vary an intensity of a drive current of a resistive heater element based on the digital control signal. The circuit includes and output circuit configured to control a respective slew rate and an electric energy dissipated in the resistive heater element independently of a resistance value of the resistive heater element.

Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.

Abstract: An antenna-in-package semiconductor device includes a semiconductor chip coupled to a planar substrate. An encapsulation body encapsulates the semiconductor chip. The encapsulation body includes a through cavity extending to the planar substrate. A rectilinear wire antenna is mounted within the through cavity and extends, for instance from the planar substrate, along an axis that is transverse to a surface of the planar substrate to which the semiconductor chip is coupled. The rectilinear wire antenna is electrically coupled to the semiconductor chip. An insulating material fills the cavity to encapsulated the rectilinear wire antenna.

Abstract: A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.

Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.

Abstract: In an embodiment a circuit includes an inertial measurement unit configured to be oscillated via a driving signal provided by driving circuitry, a lock-in amplifier configured to receive a sensing signal from the inertial measurement unit and a reference demodulation signal which is a function of the driving signal and provide an inertial measurement signal based on the sensing signal, wherein the reference demodulation signal is affected by a variable phase error, phase meter circuitry configured to receive the driving signal and the sensing signal and provide, as a function of a phase difference between the driving signal and the sensing signal, a phase correction signal for the reference demodulation signal and a correction node configured to apply the phase correction signal to the reference demodulation signal so that, in response to the phase correction signal being applied to the reference demodulation signal, the phase error is maintained in a vicinity of a reference value.

Abstract: An embodiment dashboard voice control system for a motorcycle comprises receiver circuitry to receive voice-generated signals, command recognition circuitry to recognize voice-generated command signals for a motorcycle dashboard out of the voice-generated signals received at the receiver circuitry as well as command implementation circuitry to implement motorcycle dashboard actions as a function of voice-generated command signals recognized by the command recognition circuitry.

Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.

Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage config

Abstract: A communication circuit supports a first communication protocol and a second communication protocol that is different from the first communication protocol. A number of signals include first signals conveying first information messages and second signals conveying second information messages. The first information messages include a repetitive message having fixed repeated content and the second information messages include a non-repetitive message having variable content. The first signals and the second signals are transmitted via the communication circuit using the first communication protocol for the first signals and the second communication protocol for the second signals.

Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pat gstern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.

Abstract: A method for manufacturing an optical microelectromechanical device, includes forming, in a first wafer of semiconductor material having a first surface and a second surface, a suspended mirror structure, a fixed structure surrounding the suspended mirror structure, elastic supporting elements extending between the fixed structure and the suspended mirror structure, and an actuation structure coupled to the suspended mirror structure. The method continues with forming, in a second wafer, a chamber delimited by a bottom wall having a through opening, and bonding the second wafer to the first surface of the first wafer and bonding a third wafer to the second surface of the first wafer so that the chamber overlies the actuation structure, and the through opening is aligned to the suspended mirror structure, thus forming a device composite wafer. The device composite wafer is diced to form an optical microelectromechanical device.