Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

Abstract: A method for mutual authentication that includes establishing a first inductive coupling between a wireless-power receiver and a wireless-power transmitter to transfer power from the wireless-power transmitter to the wireless-power receiver by a power signal and using the power signal to transmit a first response to a physically unclonable function to the wireless-power transmitter. The method further including generating a second response to the physically unclonable function and communicating information derived from the second response to initiate a mutual authentication process between the wireless-power receiver and the wireless-power transmitter during a subsequent inductive coupling.

Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/output register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/output register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a commands, and resumes the normal operating mode in response to a wake-up events.

Abstract: A switching regulator circuit has a high side (HS) transistor actuated during on time (TON) of a duty cycle. The output current of the switching regulator circuit is determined from sensing a transistor current flowing through the HS transistor during HS transistor on time (TON) and dividing the sensed transistor current by the duty cycle to generate an output signal indicative of the output current of the switching regulator circuit. The duty cycle is determined from a ratio of the on time (TON) and off time (TOFF) of the switching regulator circuit.

Abstract: A switching regulator circuit has a switching transistor actuated during a switching on phase of a duty cycle. The current flowing through an inductor of the switching regulator circuit is determined from sensing a transistor current flowing through the switching transistor during switching on phase and dividing the sensed transistor current by the duty cycle to generate an output signal indicative of the inductor current of the switching regulator circuit. The duty cycle is determined from a detected ratio of switching transistor turn on time during the switching on phase and switching transistor turn off time during a switching off phase as controlled by the duty cycle control of the regulator circuit.

Abstract: A charge amplifier circuit is provided. The charge amplifier circuit is couplable to a transducer that generates an electrical charge that varies with an external stimulus. The charge amplifier circuit includes an amplification stage having an input node, couplable to the transducer, and an output node. The amplification stage biases the input node at a first direct current (DC) voltage. The charge amplifier circuit includes a feedback circuit, which includes a feedback capacitor, electrically coupled between the input and output nodes of the amplification stage. The feedback circuit includes a resistor electrically coupled to the input node, and a level-shifter circuit, electrically coupled between the resistor and the output node. The level-shifter circuit biases the output node at a second DC voltage and as a function of a difference between the second DC voltage and a reference voltage.

Abstract: An optoelectronic device includes an optical integrated circuit having a first surface and a second surface opposite the first surface. The optical integrated circuit has an optical zone of the first surface of the optical integrated circuit. The device includes an electrically insulating material disposed over the optical integrated circuit, where the electrically insulating material partially covers the first surface so as to expose the optical zone.

Abstract: A control circuit includes an output terminal configured to be coupled to a control terminal of a transistor that has a current path coupled to an inductor; a transconductance amplifier configured to produce a sense current based on a current flowing through the current path of the transistor; and a first capacitor. The control circuit is configured to turn on the transistor based on a clock signal, integrate the sense current with an integrating capacitor to generate a first voltage, generate a second voltage across the first capacitor based on a first current, generate a second current based on the second voltage, generate a third voltage based on the second current, turn off the transistor when the first voltage becomes higher than the third voltage; discharge the integrating capacitor when the transistor turns off; and regulate an average output current flowing through the inductor based on the first current.

Abstract: An HS switching transistor is coupled between a high-side node and a switching node. An LS switching transistor is coupled between the switching node and a low-side node. An inductive load is coupled to the switching node in a way where one of the HS/LS switching transistors is freewheeling. In response to detection of a short circuit occurring at the switching node with the freewheeling switching transistor in the conductive state: an electrical signal at the switching node is sensed, a comparison is made between the sensed electrical signal and a threshold level, and a driving signal is provided to control freewheeling switching transistor to switch to the non-conductive state when the comparison indicates that the electrical signal has reached the threshold level.

Abstract: A semiconductor die is attached on a die-attachment portion of a planar substrate. A planar electrically conductive clip in mounted onto the semiconductor die. The semiconductor die is sandwiched between the die-attachment portion and the electrically conductive clip. A distal portion of the electrically conductive clip extending away from the semiconductor die is spaced from an electrically conductive lead of the planar substrate by a gap. This gap is filled by a mass of gap-filling material transferred to an upper surface of the electrically conductive lead via Laser Induced Forward Transfer (LIFT) processing. A mass of the gap-filling material is sized and dimensioned to substantially fill the gap.

Abstract: A synchronous rectifier driver circuit is configured to drive a synchronous rectifier FET and includes a first terminal configured to be connected to a source terminal of the synchronous rectifier FET. A second terminal is configured to be connected to a drain terminal of the synchronous rectifier FET, and a third terminal is configured to be connected to a gate terminal of the synchronous rectifier FET. The synchronous rectifier driver circuit is configured to measure the voltage between the second terminal and the first terminal, and detect a switch-on instant in which the measured voltage reaches a first threshold value and a switch-off instant in which the measured voltage reaches a second threshold value. The synchronous rectifier driver circuit generates a drive signal between the third terminal and the first terminal as a function of the measured voltage.

Abstract: An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.

Abstract: In an embodiment a timing system includes a master timing device including a master oscillator stage configured to receive a reference signal and to generate a first main clock signal frequency-locked with the reference signal, a master timing stage including a master counter configured to update value with a timing that depends on the first main clock signal, the master timing stage configured to generate a first local clock signal of a pulsed type, a timing of pulses of the first local clock signal being controllable by the master counter and a master synchronization stage configured to generate a synchronization signal synchronous with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each group of consecutive pulses of the first local clock signal formed by a number (N) of pulses, and a slave timing device including a slave oscillator stage configured to receive the reference signal and to generate a second main clock signal frequency-locked with the refer

Abstract: A semiconductor chip or die is arranged on a first surface of a thermally conductive die pad of a substrate such as a leadframe. An encapsulation of insulating material in molded onto the die pad having the semiconductor die arranged on the first surface. At the second surface of the die pad, opposite the first surface, the encapsulation borders on the die pad at a borderline around the die pad. A recessed portion of the encapsulation is provided, for example, via laser ablation, at the borderline around the die pad. Thermally conductive material such as metal material is filled in the recessed portion of the encapsulation around the die pad. The surface area of the thermally conductive die pad is augmented by the filling of thermally conductive material in the recessed portion of the encapsulation thus improving thermal performance of the device.

Abstract: A semiconductor integrated circuit chip is arranged on a first surface of a substrate that includes electrically conductive lead formations in an array, wherein the electrically conductive lead formations are covered by a masking layer at a second surface opposite the first surface. The semiconductor integrated circuit chip is electrically coupled to electrically conductive lead formations and an insulating encapsulation is molded on the semiconductor integrated circuit chip. The masking layer is then selectively removed, for example, via laser ablation, from one or more of the electrically conductive lead formations. The electrically conductive lead formations that are left uncovered by the masking layer are then removed by an etching process applied to the second surface of the substrate. The selective removal of the unmasked electrically conductive lead formations serves to increase a creepage distance between those conductive lead formations that are left in place.

Abstract: A semiconductor die is attached on a die mounting surface of a substrate. An insulating encapsulation of laser direct structuring (LDS) material is molded onto the substrate and the semiconductor die. The insulating encapsulation of LDS material has a front surface including a first portion and a second portion separated by gaps therebetween. Laser direct structuring processing is applied to the first portion of the front surface to structure in the encapsulation of LDS material electrically conductive formations including electrically conductive lines over the front surface and to the second portion of the front surface of the encapsulation of LDS material to form thereon a reinforcing warp-countering structure. The separation gaps are left exempt from laser direct structuring processing and the reinforcing warp-countering structure is electrically insulated from the electrically conductive lines by LDS material left exempt from laser direct structuring processing at the separation gaps.

Abstract: A method and device for unlatching a door from a frame, using a keyless door latch system, is provided. In one embodiment, a secondary unlocking component receives a signal and derives power from the signal to provide a power source for the keyless door latch system. A microcontroller generates a control signal and an actuator, in response to receiving the control signal, actuates the secondary unlocking component, which allows an energy source, from an exterior of the door, to be transferred to the keyless door latch system for the unlatching of the door.

Abstract: A circuit for reading or writing a RAM includes a shift register coupled to the RAM, a test data input, and a test data output. The circuit further includes a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.

Abstract: A pressure sensing device may include a body configured to distribute a load applied between first and second parts positioned one against the other, and a pressure sensor carried by the body. The pressure sensor may include a support body, and an IC die mounted with the support body and defining a cavity. The IC die may include pressure sensing circuitry responsive to bending associated with the cavity, and an IC interface coupled to the pressure sensing circuitry.

Abstract: A method of operating a radar sensor system includes: frequency down-converting a reception signal that is chirp-modulated with a sequence of chirp ramps to an intermediate frequency signal; and high-pass filtering the intermediate frequency signal to produce a high-pass filtered signal. High-pass filtering includes: first high-pass filtering, with a first corner frequency, the intermediate frequency signal at each chirp in the chirp modulation of the reception signal; and replacing the first high-pass filtering with a second high-pass filtering with a second corner frequency, the first corner frequency being higher than the second corner frequency.