Abstract: A voltage regulator includes an amplifier and a regulation loop. The regulator includes a first PMOS transistor connected to a terminal supplying an input voltage, a second PMOS transistor connected in series with the first PMOS transistor. A node between those two transistors defines an output terminal. A first source of a first polarization current of fixed value is connected to the gate of the first transistor, and a second source of a second polarization current of fixed value connects the second transistor to ground. A third NMOS transistor is connected between the two current sources. A circuit is provided to modify automatically at least one of the polarization currents in relation to the load current.

Abstract: A method for correcting mismatches between a digital signal in phase and a digital signal in quadrature originating from a signal broadcast by terrestrial channel, comprising a phase correction method. A set of first error values is measured during a first period. A current value of a second error is determined based on a sum of the first error values. The current value is compared with a previous second error value stored in memory. The value of a current phase shift correction is chosen from two phase shift correction values, based on the result of the comparison and the value of a previous phase shift correction. The value of the chosen current phase shift correction is added to the previous phase shift to obtain a current phase shift. This current phase shift is introduced between the digital signal in phase and the digital signal in quadrature.

Abstract: A method of synthesis of at least one logic device coupled between first and second supply voltages and having a plurality of inputs and an output, the logic device including a plurality of transistors having a standard gate length, the method including: identifying, in the at least one logic device, one or more transistors connected between the first or second supply voltage and the output node; and increasing the gate length of each of the identified one or more transistors.

Abstract: A reconfigurable power amplifier includes at least one amplification circuit (E1, E2), and a circuit (6) for controlling the amplification circuit so as to adapt its operation according to an applied input signal (RFin). The circuit for controlling includes a circuit (4, 5) for modifying the compression point of the amplification circuit and for adapting the gain of the amplification circuit in such a manner as to increase the power added efficiency of the circuit for the modified compression point.

Abstract: A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.

Abstract: A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch.

Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.

Abstract: A mode-switching transformer comprising a first line in common mode and a second line in differential mode, each line comprising two sections in series respectively coupled with one of the two sections of the other line and all sections having the same lengths, the common mode line being connected in series with a capacitor, to lower the central frequency of the transformer passband, the ?/4 lengths of the sections being chosen to correspond to a central frequency greater than the central frequency desired for the transformer.

Abstract: A device processes a received radio signal. Circuitry formulates voltage samples of the radio signal. Analog processing of those samples is performed. Then, digital processing is performed on the output of the analog processing. The circuitry for formulating voltage samples is configured to ensure a processing of the samples prior to the digital processing.

Abstract: A switch including a first transistor including a first main terminal connected to a first switch node, a second main terminal connected to a second switch node and a control terminal, the second switch node being connected to a first clean voltage supply, and first control circuitry connected to the control terminal of the first transistor, including a first node connected to the first clean voltage supply, a second node connected to a second voltage level, and a control input node for receiving a first input control signal variable between a supply voltage level and a third voltage level, the first control means arranged to selectively connect the control terminal of the first transistor to one of the first node and the second node based on the first input control signal.

Abstract: A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation step and a nitridation step of the cobalt-based metal material of the metal layer are performed. The antidiffusion properties of copper atoms (for example) and the antioxidation properties of the metal barrier are improved.

Abstract: A circuit is provided for clock recovery. The circuit includes a reference extraction unit for extracting from a datastream time references defining a reference time base, and a digital Phase Locked Loop including a first programmable counter in the guise of a digitally controlled oscillator for overseeing an output time base, a second programmable counter in the guise of a loop divider for overseeing a loop time base, and a dedicated processor capable of executing a program including a first software module in the guise of a phase comparator for comparing values of the loop and reference time bases and generating a loop error, and a second software module in the guise of a loop filter for producing an adaptation value of an increment value of the first programmable counter from the loop error. Also provided are a user terminal and a method for clock recovery.

Abstract: The method is for transmitting data between two devices via a clock wire or line and at least one data wire or line. The clock wire is maintained by default on a logic value A, and each device is capable of tying the clock wire to an electric potential representing a logic value B that is the opposite of A. According to the method, both devices tie the clock wire to B when a datum is transmitted, the device to which the datum is sent does not release the clock wire while it has not read the datum, and the device sending the datum maintains the datum on the data wire at least until an instant when the clock wire is released by the device to which the datum is sent. The method is particularly applicable to communication between a microcomputer and a microprocessor.

Abstract: Detection method and device for a receiver in a digital communication system designed to process a frame comprising a periodic sub-set of length n, said method comprising the following steps:—determining a first vector u having a length n;—determining a second shifted vector v;—calculating a correlation function between said first and second vectors;—calculating a quadratic error function between said first and second vectors;—calculating a first cost function that is a linear combination of both preceding functions and, according to the sign of the result,—calculating a second cost function of frame beginning estimate; and—starting the communication system receiver.

Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.

Abstract: A circuit for controlling a matrix display formed of light-emitting diodes, capable of successively selecting lines of the screen and, for each line from a set of selected lines, of selecting columns, the voltage of each selected column settling at an operating voltage. The circuit is capable, before selection of each line from said set of lines, of precharging at least the columns to be selected to a precharge voltage. The circuit includes a device for adjusting the precharge voltage including a measurement circuit capable, on each selection of a line from said set of lines, of measuring the maximum operating voltage from among the operating voltages of the selected columns; a circuit capable of storing the maximum measured operating voltage; and a circuit capable of adjusting the precharge voltage based on the maximum stored operating voltage.

Abstract: A method and an element of ciphering by an integrated processor of data to be stored in a memory, including applying a ciphering algorithm which is a function of a key specific to the integrated circuit and of an initialization vector, and of memorizing at least the ciphered data, the initialization vector depending at least on the address of storage of the data in the memory.

Abstract: A random signal generator uses a folded MOS transistor, whose drain-source current includes a random component, as an electronic noise source. The random signal generator generates a random binary signal from the random component. The invention may be applied, in particular, to smart cards.

Abstract: Circuitry for controlling a display matrix formed of light-emitting diodes arranged in rows and columns, diodes in each row being connected to common row lines, and diodes in each column being connected to common column lines, each of the column lines being selectively connected to a current source for providing a current to each of the column lines when the column line is selected, a column voltage being present at a column node of each column line while the column line is selected, each of the row lines being selectively connected to a rowoff voltage for turning off the diodes in that row, the circuitry including circuitry for generating the rowoff voltage including: capture circuitry arranged to capture a maximum value of the column voltages present at the column nodes of a plurality of selected column lines; storage circuitry arranged to store the maximum column voltage; and output circuitry arranged to provide the rowoff voltage based on the maximum column voltage.

Abstract: A method and a device for estimating a first value of a signal formed of a series of values corresponding either to the first value or to a second value equal to the opposite of the first value, where the signal can take values other than the first and second values due to noise.